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Sender: Richard Henderson <rth7680@gmail.com>
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Date: Tue, 28 Jan 2014 09:05:24 -0800
From: Richard Henderson <rth@twiddle.net>
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Subject: Re: [Qemu-devel] [PATCH 09/21] target-arm: A64: Implement SIMD
 3-reg-same shift and saturate insns
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To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: Peter Crosthwaite <peter.crosthwaite@xilinx.com>, patches@linaro.org, Michael Matz <matz@suse.de>, Alexander Graf <agraf@suse.de>, Claudio Fontana <claudio.fontana@linaro.org>, Dirk Mueller <dmueller@suse.de>, Will Newton <will.newton@linaro.org>, Laurent Desnogues <laurent.desnogues@gmail.com>, =?ISO-8859-1?Q?Alex_Benn=E9e?= <alex.bennee@linaro.org>, kvmarm@lists.cs.columbia.edu, Christoffer Dall <christoffer.dall@linaro.org>

On 01/26/2014 11:25 AM, Peter Maydell wrote:
> Implement the SIMD 3-reg-same instructions SQADD, UQADD,
> SQSUB, UQSUB, SSHL, USHL, SQSHl, UQSHL, SRSHL, URSHL,
> SQRSHL, UQRSHL; these are all simple calls to existing
> Neon helpers. We also enable SSHL, USHL, SRSHL and URSHL
> for the 3-reg-same-scalar category (but not the others
> because they can have non-size-64 operands and the
> scalar_3reg_same function doesn't support that yet.)
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target-arm/translate-a64.c | 134 +++++++++++++++++++++++++++++++++++++--------
>  1 file changed, 112 insertions(+), 22 deletions(-)

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~