From: Richard Henderson <rth@twiddle.net>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: "Peter Crosthwaite" <peter.crosthwaite@xilinx.com>,
"Laurent Desnogues" <laurent.desnogues@gmail.com>,
patches@linaro.org, "Michael Matz" <matz@suse.de>,
"Alexander Graf" <agraf@suse.de>,
"Claudio Fontana" <claudio.fontana@linaro.org>,
"Dirk Mueller" <dmueller@suse.de>,
"Will Newton" <will.newton@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>,
kvmarm@lists.cs.columbia.edu,
"Christoffer Dall" <christoffer.dall@linaro.org>
Subject: Re: [Qemu-devel] [PATCH 14/21] target-arm: A64: Implement remaining integer scalar-3-same insns
Date: Tue, 28 Jan 2014 13:01:23 -0800 [thread overview]
Message-ID: <52E81AA3.5010901@twiddle.net> (raw)
In-Reply-To: <1390764312-21789-15-git-send-email-peter.maydell@linaro.org>
On 01/26/2014 11:25 AM, Peter Maydell wrote:
> Implement the remaining integer instructions in the scalar-three-reg-same
> group: SQADD, UQADD, SQSUB, UQSUB, SQSHL, UQSHL, SQRSHL, UQRSHL,
> SQDMULH, SQRDMULH.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target-arm/translate-a64.c | 106 +++++++++++++++++++++++++++++++++++++--------
> 1 file changed, 87 insertions(+), 19 deletions(-)
Reviewed-by: Richard Henderson <rth@twiddle.net>
r~
next prev parent reply other threads:[~2014-01-28 21:01 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-26 19:24 [Qemu-devel] [PATCH 00/21] A64: Add Neon instructions, second and third sets Peter Maydell
2014-01-26 19:24 ` [Qemu-devel] [PATCH 01/21] target-arm: A64: Add SIMD three-different multiply accumulate insns Peter Maydell
2014-01-26 19:24 ` [Qemu-devel] [PATCH 02/21] target-arm: A64: Add SIMD three-different ABDL instructions Peter Maydell
2014-01-28 18:59 ` Peter Maydell
2014-01-26 19:24 ` [Qemu-devel] [PATCH 03/21] target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops Peter Maydell
2014-01-26 19:24 ` [Qemu-devel] [PATCH 04/21] target-arm: A64: Add top level decode for SIMD 3-same group Peter Maydell
2014-01-26 19:24 ` [Qemu-devel] [PATCH 05/21] target-arm: A64: Add logic ops from SIMD 3 same group Peter Maydell
2014-01-26 19:24 ` [Qemu-devel] [PATCH 06/21] target-arm: A64: Add integer ops from SIMD 3-same group Peter Maydell
2014-01-26 19:24 ` [Qemu-devel] [PATCH 07/21] target-arm: A64: Add simple SIMD 3-same floating point ops Peter Maydell
2014-01-26 19:24 ` [Qemu-devel] [PATCH 08/21] target-arm: A64: Add SIMD shift by immediate Peter Maydell
2014-01-26 19:25 ` [Qemu-devel] [PATCH 09/21] target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns Peter Maydell
2014-01-28 17:05 ` Richard Henderson
2014-01-26 19:25 ` [Qemu-devel] [PATCH 10/21] target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns Peter Maydell
2014-01-28 17:13 ` Richard Henderson
2014-01-28 17:19 ` Peter Maydell
2014-01-26 19:25 ` [Qemu-devel] [PATCH 11/21] target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD Peter Maydell
2014-01-28 17:21 ` Richard Henderson
2014-01-28 18:27 ` Peter Maydell
2014-01-26 19:25 ` [Qemu-devel] [PATCH 12/21] tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR Peter Maydell
2014-01-28 17:23 ` Richard Henderson
2014-01-26 19:25 ` [Qemu-devel] [PATCH 13/21] target-arm: A64: Implement scalar pairwise ops Peter Maydell
2014-01-28 17:28 ` Richard Henderson
2014-01-26 19:25 ` [Qemu-devel] [PATCH 14/21] target-arm: A64: Implement remaining integer scalar-3-same insns Peter Maydell
2014-01-28 21:01 ` Richard Henderson [this message]
2014-01-26 19:25 ` [Qemu-devel] [PATCH 15/21] target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc Peter Maydell
2014-01-28 17:34 ` Richard Henderson
2014-01-26 19:25 ` [Qemu-devel] [PATCH 16/21] target-arm: A64: Add skeleton decode for SIMD 2-reg misc group Peter Maydell
2014-01-28 17:40 ` Richard Henderson
2014-01-26 19:25 ` [Qemu-devel] [PATCH 17/21] target-arm: A64: Implement 2-register misc compares, ABS, NEG Peter Maydell
2014-01-28 17:44 ` Richard Henderson
2014-01-26 19:25 ` [Qemu-devel] [PATCH 18/21] target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT Peter Maydell
2014-01-28 17:47 ` Richard Henderson
2014-01-26 19:25 ` [Qemu-devel] [PATCH 19/21] target-arm: A64: Add narrowing 2-reg-misc instructions Peter Maydell
2014-01-28 20:52 ` Richard Henderson
2014-01-26 19:25 ` [Qemu-devel] [PATCH 20/21] target-arm: A64: Add 2-reg-misc REV* instructions Peter Maydell
2014-01-28 20:57 ` Richard Henderson
2014-01-26 19:25 ` [Qemu-devel] [PATCH 21/21] target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group Peter Maydell
2014-01-28 20:59 ` Richard Henderson
2014-01-26 19:33 ` [Qemu-devel] [PATCH 00/21] A64: Add Neon instructions, second and third sets Peter Maydell
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