From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH 0/4] xen/arm: fix guest builder cache cohenrency (again, again) Date: Wed, 29 Jan 2014 13:26:34 +0000 Message-ID: <52E9018A.5090908@linaro.org> References: <1390997452.31814.90.camel@kazak.uk.xensource.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1390997452.31814.90.camel@kazak.uk.xensource.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell , xen-devel Cc: Keir Fraser , George Dunlap , Tim Deegan , Ian Jackson , Julien Grall , Stefano Stabellini , Jan Beulich List-Id: xen-devel@lists.xenproject.org Hi Ian, Thanks for the patch series. On 29/01/14 12:10, Ian Campbell wrote: > Jan/Ian/Keir -- the final patch involves tools changes and a new domctl, > which is why you are copied (although the domctl is marked as arm > specific you might have opinions on it). > > On ARM we need to take care of cache coherency for guests which we have > just built because they start with their caches disabled. > > Our current strategy for dealing with this, which is to make guest > memory default to cacheable regardless of the in guest configuration > (the HCR.DC bit), is flawed because it doesn't handle guests which > enable their MMU before enabling their caches, which at least FreeBSD > does. (NB: Setting HCR.DC while the guest MMU is enabled is > UNPREDICTABLE, hence we must disable it when the guest turns its MMU > one). Enabling the cache earlier wouldn't change the issue :). The main problem is the page table attributes. Using Write-Through (with cached enabled/disabled) can randomly crash guest. -- Julien Grall