Re: [lm-sensors] Reading SPD on Intel Patsburg on Supermicro X9SRG-F board

[Guenter Roeck <linux@roeck-us.net>]

On 01/29/2014 07:39 PM, Alun Evans wrote:
>
> On 29 Jan 2014, at 17:42, Guenter Roeck <linux@roeck-us.net> wrote:
>
>> On Wed, Jan 29, 2014 at 05:30:14PM -0800, Guenter Roeck wrote:
>>> On Wed, Jan 29, 2014 at 05:12:48PM -0800, Alun Evans wrote:
>>>>
>>>> On 29 Jan 2014, at 11:48, Alun Evans <alun@badgerous.net> wrote:
>>>>
>>>>> Thanks for the responses everyone, inline,
>>>>>
>>>>> On 29 Jan 2014, at 10:25, Guenter Roeck <linux@roeck-us.net> wrote:
>>>>>
>>>>>> On Wed, Jan 29, 2014 at 05:42:24PM +0100, Jean Delvare wrote:
>>>>>>> Hi Alun,
>>>>>>> <snip>
>>>>>>
>>>>>>> Please ask Supermicro about it.
>>>>>
>>>>> I have put a request in… We’ll see if I get a response.
>>>>>
>>>>>>> If the memory slots are behind an I2C
>>>>>>> multiplexer, ask them if the multiplexer is I2C-based or GPIO-based. If
>>>>>>> I2C-based, ask for the multiplexer type and address. If GPIO-based, ask
>>>>>>> for the chip name and pin numbers for the GPIOs. In both case, please
>>>>>>> ask which GPIO combinations map to which memory slots.
>>>>
>>>> I inlined the above hunk with my question, and the first response was:
>>>>
>>>>> Received feedback; The memory address does not use mux.  It is hardware defined by Intel.
>>>>
>>>> So I went and clarified I was not talking about the DDR physical address setup by the memory reference code, and I got:
>>>>
>>>>> Per our engineer; There is no hardware connecting to DIMM.
>>>>
>>>> I’m not sure I’ve found the right help here...
>>>>
>>> Actually you might have. On some HW the DIMMs are connceted to a separate
>>> SMBus channel which is not visible to SW.
>>>
>> I had a quick glance into the Patsburg (c600) datasheet. The chip has
>> up to four SMBus channels, depending on chip variant. Are you sure
>> that you are talking to the correct one ? What do you see with lspci ?
>
> I am talking to that one:
>
> $ sudo lspci -v -v -v -s 0000:00:1f.3
> 00:1f.3 SMBus: Intel Corporation C600/X79 series chipset SMBus Host Controller (rev 05)
>          Subsystem: Super Micro Computer Inc Device 0661
>          Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
>          Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
>          Interrupt: pin C routed to IRQ 18
>          Region 0: Memory at fba20000 (64-bit, non-prefetchable) [size=256]
>          Region 4: I/O ports at 1180 [size=32]
>          Kernel driver in use: i801_smbus
>          Kernel modules: i2c-i801
>
Anything else that looks like an SMBus controller ? The datasheet says that "SRV/WS SKUs Only"
would have additional SMBus controllers.

> Whether or not the DIMMs are connected to it is a good question.
>
> It’s a C602:
> http://www.supermicro.com/products/motherboard/xeon/c600/x9srg-f.cfm
>

>
> Thinking about it, this Xeon has an integrated memory controller with 4 DDR3 channels, each of which can have 3 DIMMs per channel. That’s potentially 12 DIMMs on a board, which exceeds the 8 addressable SPDs given the 3 pins for addressing (SA{0-2}). While this board only has 8 DIMMs, it would make some sense if they were split in half with a mux somewhere.
>

Presumably there must be a means for the BIOS to read the SPD data to be able to
program the DRAM controller correctly. No idea how that works in detail, though.

Guenter


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