From: Richard Henderson <rth@twiddle.net>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: "Peter Crosthwaite" <peter.crosthwaite@xilinx.com>,
patches@linaro.org, "Michael Matz" <matz@suse.de>,
"Alexander Graf" <agraf@suse.de>,
"Claudio Fontana" <claudio.fontana@linaro.org>,
"Dirk Mueller" <dmueller@suse.de>,
"Will Newton" <will.newton@linaro.org>,
"Laurent Desnogues" <laurent.desnogues@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
kvmarm@lists.cs.columbia.edu,
"Christoffer Dall" <christoffer.dall@linaro.org>
Subject: Re: [Qemu-devel] [PATCH v2 02/13] target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns
Date: Mon, 03 Feb 2014 13:21:31 -0800 [thread overview]
Message-ID: <52F0085B.7030609@twiddle.net> (raw)
In-Reply-To: <1391295607-1426-3-git-send-email-peter.maydell@linaro.org>
On 02/01/2014 02:59 PM, Peter Maydell wrote:
> Implement the SIMD 3-reg-same instructions where the size == 3 case
> is reserved: SHADD, UHADD, SRHADD, URHADD, SHSUB, UHSUB, SMAX,
> UMAX, SMIN, UMIN, SABD, UABD, SABA, UABA, MLA, MLS, MUL, PMUL,
> SQRDMULH, SQDMULH. (None of these have scalar-3-same versions.)
> This completes the non-pairwise integer instructions in this category.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
r~
next prev parent reply other threads:[~2014-02-03 21:21 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-01 22:59 [Qemu-devel] [PATCH v2 00/13] A64: Add Neon instructions, third set Peter Maydell
2014-02-01 22:59 ` [Qemu-devel] [PATCH v2 01/13] target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns Peter Maydell
2014-02-01 22:59 ` [Qemu-devel] [PATCH v2 02/13] target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same insns Peter Maydell
2014-02-03 21:21 ` Richard Henderson [this message]
2014-02-01 22:59 ` [Qemu-devel] [PATCH v2 03/13] target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD Peter Maydell
2014-02-01 22:59 ` [Qemu-devel] [PATCH v2 04/13] tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR Peter Maydell
2014-02-01 22:59 ` [Qemu-devel] [PATCH v2 05/13] target-arm: A64: Implement scalar pairwise ops Peter Maydell
2014-02-01 23:00 ` [Qemu-devel] [PATCH v2 06/13] target-arm: A64: Implement remaining integer scalar-3-same insns Peter Maydell
2014-02-01 23:00 ` [Qemu-devel] [PATCH v2 07/13] target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc Peter Maydell
2014-02-01 23:00 ` [Qemu-devel] [PATCH v2 08/13] target-arm: A64: Add skeleton decode for SIMD 2-reg misc group Peter Maydell
2014-02-01 23:00 ` [Qemu-devel] [PATCH v2 09/13] target-arm: A64: Implement 2-register misc compares, ABS, NEG Peter Maydell
2014-02-01 23:00 ` [Qemu-devel] [PATCH v2 10/13] target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT Peter Maydell
2014-02-01 23:00 ` [Qemu-devel] [PATCH v2 11/13] target-arm: A64: Add narrowing 2-reg-misc instructions Peter Maydell
2014-02-01 23:00 ` [Qemu-devel] [PATCH v2 12/13] target-arm: A64: Add 2-reg-misc REV* instructions Peter Maydell
2014-02-03 21:23 ` Richard Henderson
2014-02-01 23:00 ` [Qemu-devel] [PATCH v2 13/13] target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group Peter Maydell
2014-02-03 23:34 ` [Qemu-devel] [PATCH v2 00/13] A64: Add Neon instructions, third set Peter Maydell
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