From mboxrd@z Thu Jan  1 00:00:00 1970
From: Mugunthan V N <mugunthanvnm@ti.com>
Subject: Re: TI CPSW Ethernet Tx performance regression
Date: Tue, 4 Feb 2014 14:16:22 +0530
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Cc: netdev <netdev@vger.kernel.org>,
	Ben Hutchings <ben@decadent.org.uk>
To: Florian Fainelli <f.fainelli@gmail.com>
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Hi

On Tuesday 04 February 2014 12:54 AM, Florian Fainelli wrote:
> Ok,the priv pointer when we enter the interrupt handler could point to
> e.g: slave 0, so we need to get it re-assigned to the second slave
> using cpsw_get_slave_priv(). How do you ensure that "priv" at the
> beginning of the interrupt handler does not already point to slave 1?
> In that case, is not there a chance to starve slave 0, or at least
> cause an excessive latency by exiting the interrupt handler for slave
> 1, and then re-entering it for slave 0?

devm_request_irq is called with slave 0 priv, so at the beginning of the
interrupt it is always slave 0 priv irrespective whether the slave 0
interface is up or not.

Regards
Mugunthan V N