From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33250) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WCrGo-0001rS-Py for qemu-devel@nongnu.org; Mon, 10 Feb 2014 08:51:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WCrGh-0005ey-PU for qemu-devel@nongnu.org; Mon, 10 Feb 2014 08:51:34 -0500 Received: from cantor2.suse.de ([195.135.220.15]:39812 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WCrGh-0005er-En for qemu-devel@nongnu.org; Mon, 10 Feb 2014 08:51:27 -0500 Message-ID: <52F8D95B.7000606@suse.de> Date: Mon, 10 Feb 2014 14:51:23 +0100 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1390580324-1924-1-git-send-email-petar.jovanovic@rt-rk.com> <1390580324-1924-2-git-send-email-petar.jovanovic@rt-rk.com> In-Reply-To: <1390580324-1924-2-git-send-email-petar.jovanovic@rt-rk.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Petar Jovanovic , qemu-devel@nongnu.org Cc: petar.jovanovic@imgtec.com, aurelien@aurel32.net Am 24.01.2014 17:18, schrieb Petar Jovanovic: > From: Petar Jovanovic >=20 > Add mips32r5-generic among CPU definitions for MIPS. > Define ISA_MIPS32R3 and ISA_MIPS32R5. >=20 > Signed-off-by: Petar Jovanovic > --- > target-mips/mips-defs.h | 8 ++++++++ > target-mips/translate_init.c | 25 +++++++++++++++++++++++++ > 2 files changed, 33 insertions(+) >=20 > diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h > index bf094a3..9dfa516 100644 > --- a/target-mips/mips-defs.h > +++ b/target-mips/mips-defs.h > @@ -29,6 +29,8 @@ > #define ISA_MIPS32R2 0x00000040 > #define ISA_MIPS64 0x00000080 > #define ISA_MIPS64R2 0x00000100 > +#define ISA_MIPS32R3 0x00000200 > +#define ISA_MIPS32R5 0x00000400 > =20 > /* MIPS ASEs. */ > #define ASE_MIPS16 0x00001000 > @@ -64,6 +66,12 @@ > #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) > #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) > =20 > +/* MIPS Technologies "Release 3" */ > +#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) > + > +/* MIPS Technologies "Release 5" */ > +#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5) > + > /* Strictly follow the architecture standard: > - Disallow "special" instruction handling for PMON/SPIM. > Note that we still maintain Count/Compare to match the host clock. = */ > diff --git a/target-mips/translate_init.c b/target-mips/translate_init.= c > index c45b1b2..d74a0af 100644 > --- a/target-mips/translate_init.c > +++ b/target-mips/translate_init.c > @@ -333,6 +333,31 @@ static const mips_def_t mips_defs[] =3D > .insn_flags =3D CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR= 2, > .mmu_type =3D MMU_TYPE_R4000, > }, > + { > + /* A generic CPU providing MIPS32 Release 5 features. > + FIXME: Eventually this should be replaced by a real CPU mod= el. */ That is not really possible. QEMU needs to keep command line backwards compatibility, so if you add a generic model now, we will need to live with the generic model for a long time. What's the difficulty with taking "a real CPU model"? Is there no silicon yet or just a code name rather than a marketing name? Otherwise the patch looks okay. Regards, Andreas P.S. If you want to ping a patch series, please ping the cover letter. Sorry it's been taking so long, I'll provide my promised comments on the KVM series right now... > + .name =3D "mips32r5-generic", > + .CP0_PRid =3D 0x00019700, > + .CP0_Config0 =3D MIPS_CONFIG0 | (0x1 << CP0C0_AR) | > + (MMU_TYPE_R4000 << CP0C0_MT), > + .CP0_Config1 =3D MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1= _MMU) | > + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1= _IA) | > + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1= _DA) | > + (1 << CP0C1_CA), > + .CP0_Config2 =3D MIPS_CONFIG2, > + .CP0_Config3 =3D MIPS_CONFIG3, > + .CP0_LLAddr_rw_bitmask =3D 0, > + .CP0_LLAddr_shift =3D 4, > + .SYNCI_Step =3D 32, > + .CCRes =3D 2, > + .CP0_Status_rw_bitmask =3D 0x3778FF1F, > + .CP1_fcr0 =3D (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) = | > + (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID= ), > + .SEGBITS =3D 32, > + .PABITS =3D 32, > + .insn_flags =3D CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR= 2, > + .mmu_type =3D MMU_TYPE_R4000, > + }, > #if defined(TARGET_MIPS64) > { > .name =3D "R4000", >=20 --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg