From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47285) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WD812-0003Pb-NO for qemu-devel@nongnu.org; Tue, 11 Feb 2014 02:44:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WD80v-0007QW-Cm for qemu-devel@nongnu.org; Tue, 11 Feb 2014 02:44:24 -0500 Received: from mail-pa0-f52.google.com ([209.85.220.52]:53169) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WD80v-0007QC-6k for qemu-devel@nongnu.org; Tue, 11 Feb 2014 02:44:17 -0500 Received: by mail-pa0-f52.google.com with SMTP id bj1so7293217pad.25 for ; Mon, 10 Feb 2014 23:44:16 -0800 (PST) Message-ID: <52F9D4C9.4000107@ozlabs.ru> Date: Tue, 11 Feb 2014 18:44:09 +1100 From: Alexey Kardashevskiy MIME-Version: 1.0 References: <1390369426-6462-1-git-send-email-aik@ozlabs.ru> <1390369426-6462-4-git-send-email-aik@ozlabs.ru> <87ob33hzn9.fsf@linux.vnet.ibm.com> In-Reply-To: <87ob33hzn9.fsf@linux.vnet.ibm.com> Content-Type: text/plain; charset=KOI8-R Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v3 3/3] spapr-hcall: add address-translation-mode-on-interrupt resource in H_SET_MODE List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Aneesh Kumar K.V" , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org On 01/23/2014 07:26 PM, Aneesh Kumar K.V wrote: > Alexey Kardashevskiy writes: > >> This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from >> the H_SET_MODE, for POWER8 (PowerISA 2.07) only. >> >> Signed-off-by: Alexey Kardashevskiy >> --- >> hw/ppc/spapr_hcall.c | 26 ++++++++++++++++++++++++++ >> target-ppc/cpu.h | 2 ++ >> 2 files changed, 28 insertions(+) >> >> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c >> index b21d74b..7e4fc5f 100644 >> --- a/hw/ppc/spapr_hcall.c >> +++ b/hw/ppc/spapr_hcall.c >> @@ -721,6 +721,32 @@ static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr, >> default: >> ret = H_UNSUPPORTED_FLAG; >> } >> + } else if (resource == H_SET_MODE_RESOURCE_ADDR_TRANS_MODE) { >> + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); >> + >> + if (!(pcc->insns_flags2 & PPC2_ISA207S)) { >> + return H_P2; >> + } >> + if (value1) { >> + ret = H_P3; >> + goto out; >> + } >> + if (value2) { >> + ret = H_P4; >> + goto out; >> + } >> + switch (mflags) { >> + case 0: > > Shouldn't case 0 clear the LPCR_AIL bit ? Does not it? >> + case 2: >> + case 3: >> + CPU_FOREACH(cs) { >> + set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SH, LPCR_AIL); >> + } >> + return H_SUCCESS; >> + >> + default: >> + return H_UNSUPPORTED_FLAG; >> + } >> } >> > > -aneesh > -- Alexey