From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49961) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WDvuP-00075E-87 for qemu-devel@nongnu.org; Thu, 13 Feb 2014 08:00:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WDvuG-0002Ho-9i for qemu-devel@nongnu.org; Thu, 13 Feb 2014 08:00:53 -0500 Received: from host-82-135-62-35.customer.m-online.net ([82.135.62.35]:46478 helo=mail.embedded-brains.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WDvuF-0002Gu-T8 for qemu-devel@nongnu.org; Thu, 13 Feb 2014 08:00:44 -0500 Message-ID: <52FCC1F3.9020205@embedded-brains.de> Date: Thu, 13 Feb 2014 14:00:35 +0100 From: Sebastian Huber MIME-Version: 1.0 References: <1392285137-10598-1-git-send-email-sebastian.huber@embedded-brains.de> <52FCB414.2050306@adacore.com> In-Reply-To: <52FCB414.2050306@adacore.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v2] SPARC: Add and use CPU_FEATURE_CASA List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Fabien Chouteau Cc: blauwirbel@gmail.com, qemu-devel@nongnu.org On 2014-02-13 13:01, Fabien Chouteau wrote: > On 02/13/2014 10:52 AM, Sebastian Huber wrote: >> The LEON3 processor has support for the CASA instruction which is >> normally only available for SPARC V9 processors. Binutils 2.24 >> and GCC 4.9 will support this instruction for LEON3. GCC uses it to >> generate C11 atomic operations. >> >> The CAS synthetic instruction uses an ASI of 0x80. If TARGET_SPARC64 = is >> not defined use a supervisor data load/store for an ASI of 0x80 in >> helper_ld_asi()/helper_st_asi(). >> > > Hello Sebastian, > > If I understand correctly, the difference with V1 is that ASI 0x80. Why > did you chose Supervisor data access against User data access? User data access would work also. I don't have a preference here. > (I cannot > find documentation about 0x80 ASI) GCC will generate CAS instructions, e.g. .file "ticket.c" .section ".text" .align 4 .global acquire .type acquire, #function .proc 020 acquire: ld [%o0], %g1 mov %g1, %g2 .LL7: add %g1, 1, %g1 cas [%o0], %g2, %g1 cmp %g1, %g2 bne,a .LL7 mov %g1, %g2 add %o0, 4, %o0 .LL4: ld [%o0], %g1 cmp %g1, %g2 bne .LL4 nop jmp %o7+8 nop .size acquire, .-acquire .align 4 .global release .type release, #function .proc 020 release: ld [%o0+4], %g1 add %g1, 1, %g1 st %g1, [%o0+4] jmp %o7+8 nop .size release, .-release .ident "GCC: (GNU) 4.9.0 20130917 (experimental)" In the GNU Binutils you find: opcodes/sparc-opc.c:{ "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c,=20 ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, 0, v9andleon }, /* casa [rs1]ASI_P,rs= 2,rd */ This is where the 0x80 comes from. --=20 Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Puchheim, Germany Phone : +49 89 189 47 41-16 Fax : +49 89 189 47 41-09 E-Mail : sebastian.huber@embedded-brains.de PGP : Public key available on request. Diese Nachricht ist keine gesch=E4ftliche Mitteilung im Sinne des EHUG.