From mboxrd@z Thu Jan  1 00:00:00 1970
From: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>
Subject: Re: [PATCH V4.1] mcheck,
 vmce: Allow vmce_amd_* functions to handle AMD  thresolding MSRs
Date: Thu, 13 Feb 2014 11:27:21 -0600
Message-ID: <52FD0079.8050601@amd.com>
References: <1392247608-6960-1-git-send-email-aravind.gopalakrishnan@amd.com>
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To: Jan Beulich <JBeulich@suse.com>
Cc: jinsong.liu@intel.com, boris.ostrovsky@oracle.com, chegger@amazon.de, suravee.suthikulpanit@amd.com, xen-devel@lists.xen.org
List-Id: xen-devel@lists.xenproject.org

On 2/13/2014 2:38 AM, Jan Beulich wrote:
>>     *val = 0;
>>   
>> -    switch ( msr & (MSR_IA32_MC0_CTL | 3) )
>> +    /* Allow only first 3 MC banks into switch() */
>> +    switch ( msr & (-MSR_IA32_MC0_CTL | 3) )
>>       {
>>       case MSR_IA32_MC0_CTL:
>>           /* stick all 1's to MCi_CTL */
> I'm confused: You now add a comment as if the mask was including
> bit 4, which it doesn't. What am I missing?

Darn. Sorry about that. Will fix..
> Also, please get used to mention (commonly at the bottom of the
> commit message, after a --- separator) what changed compared to
> the previous iteration.
>
>
Okay, will do.

-Aravind.