From: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: jinsong.liu@intel.com, boris.ostrovsky@oracle.com,
chegger@amazon.de, suravee.suthikulpanit@amd.com,
xen-devel@lists.xen.org
Subject: Re: [PATCH V4.1] mcheck, vmce: Allow vmce_amd_* functions to handle AMD thresolding MSRs
Date: Thu, 13 Feb 2014 12:24:12 -0600 [thread overview]
Message-ID: <52FD0DCC.1030904@amd.com> (raw)
In-Reply-To: <52FD0079.8050601@amd.com>
On 2/13/2014 11:27 AM, Aravind Gopalakrishnan wrote:
> On 2/13/2014 2:38 AM, Jan Beulich wrote:
>>> *val = 0;
>>> - switch ( msr & (MSR_IA32_MC0_CTL | 3) )
>>> + /* Allow only first 3 MC banks into switch() */
>>> + switch ( msr & (-MSR_IA32_MC0_CTL | 3) )
>>> {
>>> case MSR_IA32_MC0_CTL:
>>> /* stick all 1's to MCi_CTL */
>> I'm confused: You now add a comment as if the mask was including
>> bit 4, which it doesn't. What am I missing?
>
> Darn. Sorry about that. Will fix..
Jan,
Do let me know if the following wording is fine:
/*
* Apply mask to allow bits[0:1] (necessary to uniquely identify MC0)
* MC1 is handled by virtue of 'bank' value.
*/
If not, I'm open to suggestions:)
Thanks,
-Aravind.
next prev parent reply other threads:[~2014-02-13 18:24 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-12 23:26 [PATCH V4.1] mcheck, vmce: Allow vmce_amd_* functions to handle AMD thresolding MSRs Aravind Gopalakrishnan
2014-02-13 8:38 ` Jan Beulich
2014-02-13 17:27 ` Aravind Gopalakrishnan
2014-02-13 18:24 ` Aravind Gopalakrishnan [this message]
2014-02-14 8:28 ` Jan Beulich
2014-02-16 14:47 ` Liu, Jinsong
2014-02-18 4:25 ` Liu, Jinsong
2014-02-18 9:41 ` Jan Beulich
2014-02-18 10:52 ` Liu, Jinsong
2014-02-18 11:02 ` Jan Beulich
2014-02-18 11:42 ` Liu, Jinsong
2014-02-18 12:36 ` Jan Beulich
2014-02-18 12:42 ` Liu, Jinsong
2014-02-18 16:23 ` Aravind Gopalakrishnan
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