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Date: Fri, 14 Feb 2014 17:22:11 +0100
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Subject: Re: [Qemu-devel] [PATCH v4] target-sparc: Add and use
	CPU_FEATURE_CASA
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To: Sebastian Huber <sebastian.huber@embedded-brains.de>, qemu-devel@nongnu.org
Cc: blauwirbel@gmail.com, Fabien Chouteau <chouteau@adacore.com>

Am 14.02.2014 17:06, schrieb Sebastian Huber:
> The LEON3 processor has support for the CASA instruction which is
> normally only available for SPARC V9 processors.  Binutils 2.24
> and GCC 4.9 will support this instruction for LEON3.  GCC uses it to
> generate C11 atomic operations.
>=20
> The CAS synthetic instruction uses an ASI of 0x80.  If TARGET_SPARC64 i=
s
> not defined use a supervisor data load/store for an ASI of 0x80 in
> helper_ld_asi()/helper_st_asi().  The supervisor data load/store was
> choosen according to the LEON3 documentation.
>=20
> The ASI 0x80 is defined in the SPARC V9 manual, Table 12=E2=80=94Addres=
s Space
> Identifiers (ASIs).  Here we have: 0x80, ASI_PRIMARY, Unrestricted
> access, Primary address space.
>=20
> Tested with the following program:
>=20
>   #include <assert.h>
>   #include <stdatomic.h>
>=20
>   void test(void)
>   {
>     atomic_int a;
>     int e;
>     _Bool b;
>=20
>     atomic_store(&a, 1);
>     e =3D 1;
>     b =3D atomic_compare_exchange_strong(&a, &e, 2);
>     assert(b);
>     assert(atomic_load(&a) =3D=3D 2);
>=20
>     atomic_store(&a, 3);
>     e =3D 4;
>     b =3D atomic_compare_exchange_strong(&a, &e, 5);
>     assert(!b);
>     assert(atomic_load(&a) =3D=3D 3);
>   }
>=20
> Tested also on a NGMP board with a LEON4 processor.
>=20
> v4: Fix coding style.
>=20
> Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
> Reviewed-by: Fabien Chouteau <chouteau@adacore.com>

Reviewed-by: Andreas F=C3=A4rber <afaerber@suse.de>

but please put change logs below --- next time. No v5 needed for that,
committer can fix.
Also in my theory your Signed-off-by should be last when you submit a
patch, in particular when you apply changes on top of what a reviewer
has reviewed.

Thanks,
Andreas

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