RE: [PATCH v2 3/4] gpio: realtek: Add driver for Realtek DHC RTD1625 SoC

["Yu-Chun Lin [林祐君]" <eleanor.lin@realtek.com>]

Hi Bart,

> On Wed, 8 Apr 2026 04:52:42 +0200, Yu-Chun Lin <eleanor.lin@realtek.com>
> said:
> > From: Tzuyi Chang <tychang@realtek.com>
> >
> > Add support for the GPIO controller found on Realtek DHC RTD1625 SoCs.
> >
> > Unlike the existing Realtek GPIO driver (drivers/gpio/gpio-rtd.c),
> > which manages pins via shared bank registers, the RTD1625 introduces a
> > per-pin register architecture. Each GPIO line now has its own
> > dedicated 32-bit control register to manage configuration
> > independently, including direction, output value, input value,
> > interrupt enable, and debounce. Therefore, this distinct hardware
> > design requires a separate driver.
> >
> > Reviewed-by: Linus Walleij <linusw@kernel.org>
> > Signed-off-by: Tzuyi Chang <tychang@realtek.com>
> > Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
> > ---
> > Changes in v2:
> > - Remove "default y".
> > - Add base_offset member to struct rtd1625_gpio_info to handle merged
> regions.
> > ---
> >  drivers/gpio/Kconfig        |  11 +
> >  drivers/gpio/Makefile       |   1 +
> >  drivers/gpio/gpio-rtd1625.c | 584
> > ++++++++++++++++++++++++++++++++++++
> >  3 files changed, 596 insertions(+)
> >  create mode 100644 drivers/gpio/gpio-rtd1625.c
> >
> > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index
> > 5ee11a889867..281549ad72ac 100644
> > --- a/drivers/gpio/Kconfig
> > +++ b/drivers/gpio/Kconfig
> > @@ -638,6 +638,17 @@ config GPIO_RTD
> >         Say yes here to support GPIO functionality and GPIO interrupt on
> >         Realtek DHC SoCs.
> >
> > +config GPIO_RTD1625
> > +     tristate "Realtek DHC RTD1625 GPIO support"
> > +     depends on ARCH_REALTEK || COMPILE_TEST
> > +     select GPIOLIB_IRQCHIP
> > +     help
> > +       This option enables support for the GPIO controller on Realtek
> > +       DHC (Digital Home Center) RTD1625 SoC.
> > +
> > +       Say yes here to support both basic GPIO line functionality
> > +       and GPIO interrupt handling capabilities for this platform.
> > +
> >  config GPIO_SAMA5D2_PIOBU
> >       tristate "SAMA5D2 PIOBU GPIO support"
> >       depends on MFD_SYSCON
> > diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index
> > c05f7d795c43..c95ba218d53a 100644
> > --- a/drivers/gpio/Makefile
> > +++ b/drivers/gpio/Makefile
> > @@ -159,6 +159,7 @@ obj-$(CONFIG_GPIO_REALTEK_OTTO)
> += gpio-realtek-otto.o
> >  obj-$(CONFIG_GPIO_REG)                       += gpio-reg.o
> >  obj-$(CONFIG_GPIO_ROCKCHIP)  += gpio-rockchip.o
> >  obj-$(CONFIG_GPIO_RTD)                       += gpio-rtd.o
> > +obj-$(CONFIG_GPIO_RTD1625)           += gpio-rtd1625.o
> >  obj-$(CONFIG_ARCH_SA1100)            += gpio-sa1100.o
> >  obj-$(CONFIG_GPIO_SAMA5D2_PIOBU)     += gpio-sama5d2-piobu.o
> >  obj-$(CONFIG_GPIO_SCH311X)           += gpio-sch311x.o
> > diff --git a/drivers/gpio/gpio-rtd1625.c b/drivers/gpio/gpio-rtd1625.c
> > new file mode 100644 index 000000000000..bcc1bbb115fa
> > --- /dev/null
> > +++ b/drivers/gpio/gpio-rtd1625.c
> > @@ -0,0 +1,584 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later
> > +/*
> > + * Realtek DHC RTD1625 gpio driver
> > + *
> > + * Copyright (c) 2023 Realtek Semiconductor Corp.
> 
> No modifications since 2023?
> 

Will include 2026.

> > + */
> > +
> > +#include <linux/bitfield.h>
> > +#include <linux/bitops.h>
> > +#include <linux/gpio/driver.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/irqchip.h>
> > +#include <linux/irqchip/chained_irq.h> #include <linux/irqdomain.h>
> > +#include <linux/module.h> #include <linux/platform_device.h> #include
> > +<linux/property.h> #include <linux/spinlock.h> #include
> > +<linux/types.h>
> > +
> > +#define RTD1625_GPIO_DIR BIT(0)
> > +#define RTD1625_GPIO_OUT BIT(2)
> > +#define RTD1625_GPIO_IN BIT(4)
> > +#define RTD1625_GPIO_EDGE_INT_DP BIT(6) #define
> > +RTD1625_GPIO_EDGE_INT_EN BIT(8) #define
> RTD1625_GPIO_LEVEL_INT_EN
> > +BIT(16) #define RTD1625_GPIO_LEVEL_INT_DP BIT(18) #define
> > +RTD1625_GPIO_DEBOUNCE GENMASK(30, 28) #define
> > +RTD1625_GPIO_DEBOUNCE_WREN BIT(31)
> > +
> > +#define RTD1625_GPIO_WREN(x) ((x) << 1)
> > +
> > +/* Write-enable masks for all GPIO configs and reserved hardware bits
> > +*/ #define RTD1625_ISO_GPIO_WREN_ALL 0x8000aa8a #define
> > +RTD1625_ISOM_GPIO_WREN_ALL 0x800aaa8a
> > +
> > +#define RTD1625_GPIO_DEBOUNCE_1US 0
> > +#define RTD1625_GPIO_DEBOUNCE_10US 1
> > +#define RTD1625_GPIO_DEBOUNCE_100US 2 #define
> > +RTD1625_GPIO_DEBOUNCE_1MS 3 #define
> RTD1625_GPIO_DEBOUNCE_10MS 4
> > +#define RTD1625_GPIO_DEBOUNCE_20MS 5 #define
> > +RTD1625_GPIO_DEBOUNCE_30MS 6 #define
> RTD1625_GPIO_DEBOUNCE_50MS 7
> > +
> > +#define GPIO_CONTROL(gpio) ((gpio) * 4)
> > +
> > +/**
> > + * struct rtd1625_gpio_info - Specific GPIO register information
> > + * @num_gpios: The number of GPIOs
> > + * @irq_type_support: Supported IRQ types
> > + * @gpa_offset: Offset for GPIO assert interrupt status registers
> > + * @gpda_offset: Offset for GPIO deassert interrupt status registers
> > + * @level_offset: Offset of level interrupt status register
> > + * @write_en_all: Write-enable mask for all configurable bits  */
> > +struct rtd1625_gpio_info {
> > +     unsigned int    num_gpios;
> > +     unsigned int    irq_type_support;
> > +     unsigned int    base_offset;
> > +     unsigned int    gpa_offset;
> > +     unsigned int    gpda_offset;
> > +     unsigned int    level_offset;
> > +     unsigned int    write_en_all;
> > +};
> 
> Please remove the tabs in the above struct.
> 

Ack.

> > +
> > +struct rtd1625_gpio {
> > +     struct gpio_chip                gpio_chip;
> > +     const struct rtd1625_gpio_info  *info;
> > +     void __iomem                    *base;
> > +     void __iomem                    *irq_base;
> > +     unsigned int                    irqs[3];
> > +     raw_spinlock_t                  lock;
> > +     unsigned int                    *save_regs;
> > +};
> 
> I'd also personally remove these tabs here but won't die on that hill.
> 

Ack.

> > +
> > +static unsigned int rtd1625_gpio_gpa_offset(struct rtd1625_gpio
> > +*data, unsigned int offset) {
> > +     return data->info->gpa_offset + ((offset / 32) * 4); }
> > +
> > +static unsigned int rtd1625_gpio_gpda_offset(struct rtd1625_gpio
> > +*data, unsigned int offset) {
> > +     return data->info->gpda_offset + ((offset / 32) * 4); }
> > +
> > +static unsigned int rtd1625_gpio_level_offset(struct rtd1625_gpio
> > +*data, unsigned int offset) {
> > +     return data->info->level_offset + ((offset / 32) * 4); }
> 
> Looking at these, I'm under the impression that this driver could quite easily be
> converted to using gpio-mmio or even gpio-regmap with an MMIO regmap,
> have you looked into it by any chance?
> 
> Bart


We did look into gpio-mmio and gpio-regmap, but they are not quite suitable for
our platform due to the specific hardware design:

1. Per-GPIO Dedicated Registers: Unlike typical GPIO controllers that pack 32 pins
into a single 32-bit register (1 bit per pin), our hardware uses a dedicated 32-bit
register for each individual GPIO. This single register controls the
input/output state, direction, and interrupt trigger type for that specific pin.

2. Write-Enable (WREN) Mask Mechanism: Our hardware requires a specific Write-Enable
mask to be written simultaneously when updating the register values.

3. Hardware Debounce: We also need to support hardware debounce settings per pin,
which requires custom configuration via set_config mapped to these specific per-pin
registers.

Because of these hardware constraints, manually implementing the gpio_chip callbacks
seems to be the most straightforward

Best Regards,
Yu-Chun