diff for duplicates of <53032C14.9020502@free-electrons.com> diff --git a/a/1.txt b/N1/1.txt index 43027ef..0589e01 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -93,10 +93,3 @@ Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com --------------- next part -------------- -A non-text attachment was scrubbed... -Name: 0001-RFC-clk-mvebu-make-clock-output-names-mandatory.patch -Type: text/x-diff -Size: 4907 bytes -Desc: not available -URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140218/aa2cea05/attachment.bin> diff --git a/N1/2.hdr b/N1/2.hdr new file mode 100644 index 0000000..719eabb --- /dev/null +++ b/N1/2.hdr @@ -0,0 +1,5 @@ +Content-Type: text/x-diff; + name="0001-RFC-clk-mvebu-make-clock-output-names-mandatory.patch" +Content-Transfer-Encoding: 7bit +Content-Disposition: attachment; + filename*0="0001-RFC-clk-mvebu-make-clock-output-names-mandatory.patch" diff --git a/N1/2.txt b/N1/2.txt new file mode 100644 index 0000000..a7472f9 --- /dev/null +++ b/N1/2.txt @@ -0,0 +1,127 @@ +>From ca82f66b8fbb8247b0ec2c407726105e1e1af419 Mon Sep 17 00:00:00 2001 +From: Gregory CLEMENT <gregory.clement@free-electrons.com> +Date: Tue, 18 Feb 2014 10:38:08 +0100 +Subject: [PATCH] [RFC] clk:mvebu: make clock-output-names mandatory + +Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> +--- + .../devicetree/bindings/clock/mvebu-core-clock.txt | 7 ++-- + arch/arm/boot/dts/armada-370.dtsi | 1 + + drivers/clk/mvebu/common.c | 38 +++++++++++++++------- + 3 files changed, 31 insertions(+), 15 deletions(-) + +diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt +index 307a503c5db8..4f2e3953b6a6 100644 +--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt ++++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt +@@ -40,16 +40,15 @@ Required properties: + "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC + - reg : shall be the register address of the Sample-At-Reset (SAR) register + - #clock-cells : from common clock binding; shall be set to 1 +- +-Optional properties: +-- clock-output-names : from common clock binding; allows overwrite default clock +- output names ("tclk", "cpuclk", "l2clk", "ddrclk") ++- clock-output-names : from common clock binding; should be the clock ++ output names given above + + Example: + + core_clk: core-clocks@d0214 { + compatible = "marvell,dove-core-clock"; + reg = <0xd0214 0x4>; ++ clock-output-names = "tclk", "cpuclk", "l2clk", "ddrclk"; + #clock-cells = <1>; + }; + +diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi +index af1f11e9e5a0..0d5853d05bd6 100644 +--- a/arch/arm/boot/dts/armada-370.dtsi ++++ b/arch/arm/boot/dts/armada-370.dtsi +@@ -196,6 +196,7 @@ + coreclk: mvebu-sar@18230 { + compatible = "marvell,armada-370-core-clock"; + reg = <0x18230 0x08>; ++ clock-output-names = "tclk", "cpuclk", "nbclk", "hclk", "dramclk"; + #clock-cells = <1>; + }; + +diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c +index 25ceccf939ad..5e7c9274e4d3 100644 +--- a/drivers/clk/mvebu/common.c ++++ b/drivers/clk/mvebu/common.c +@@ -51,16 +51,21 @@ void __init mvebu_coreclk_setup(struct device_node *np, + } + + /* Register TCLK */ +- of_property_read_string_index(np, "clock-output-names", 0, +- &tclk_name); ++ if (of_property_read_string_index(np, "clock-output-names", 0, ++ &tclk_name)) ++ pr_err("%s[0]: clock-output-names is mandatory\n" ++ "\"%s\" will be used by default\n", np->name, tclk_name); + rate = desc->get_tclk_freq(base); + clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL, + CLK_IS_ROOT, rate); + WARN_ON(IS_ERR(clk_data.clks[0])); + + /* Register CPU clock */ +- of_property_read_string_index(np, "clock-output-names", 1, +- &cpuclk_name); ++ if (of_property_read_string_index(np, "clock-output-names", 1, ++ &cpuclk_name)) ++ pr_err("%s[1]: clock-output-names is mandatory\n" ++ "\"%s\" will be used by default\n", ++ np->name, cpuclk_name); + rate = desc->get_cpu_freq(base); + clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL, + CLK_IS_ROOT, rate); +@@ -71,8 +76,11 @@ void __init mvebu_coreclk_setup(struct device_node *np, + const char *rclk_name = desc->ratios[n].name; + int mult, div; + +- of_property_read_string_index(np, "clock-output-names", +- 2+n, &rclk_name); ++ if (of_property_read_string_index(np, "clock-output-names", ++ 2+n, &rclk_name)) ++ pr_err("%s[%d]:clock-output-names is mandatory\n" ++ "\"%s\" will be used by default\n", ++ np->name, 2+n, rclk_name); + desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div); + clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name, + cpuclk_name, 0, mult, div); +@@ -119,19 +127,27 @@ void __init mvebu_clk_gating_setup(struct device_node *np, + const struct clk_gating_soc_desc *desc) + { + struct clk_gating_ctrl *ctrl; +- struct clk *clk; + void __iomem *base; + const char *default_parent = NULL; + int n; ++ struct of_phandle_args clkspec; + + base = of_iomap(np, 0); + if (WARN_ON(!base)) + return; + +- clk = of_clk_get(np, 0); +- if (!IS_ERR(clk)) { +- default_parent = __clk_get_name(clk); +- clk_put(clk); ++ if (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", 0, &clkspec)) { ++ of_property_read_string_index(clkspec.np, "clock-output-names", ++ clkspec.args_count ? clkspec.args[0] : 0, ++ &default_parent); ++ if (WARN_ON(default_parent == NULL)) { ++ pr_err("%s: The clock-output-names of the parent clock is mandatory.\n" ++ "%s: As this proprety is missing, this parent will be ignored.\n" ++ "%s: The tclk clock will be used as parent clock\n", ++ np->name, np->name, np->name); ++ default_parent = "tclk"; ++ } ++ of_node_put(clkspec.np); + } + + ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); +-- +1.8.1.2 diff --git a/a/content_digest b/N1/content_digest index 3d88779..75febf0 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -7,11 +7,19 @@ "ref\020140217154421.GD2765@localhost\0" "ref\0530231C5.8090905@free-electrons.com\0" "ref\020140217181902.GG2765@localhost\0" - "From\0gregory.clement@free-electrons.com (Gregory CLEMENT)\0" - "Subject\0[PATCH 0/4] clk: mvebu: fix clk init order\0" + "From\0Gregory CLEMENT <gregory.clement@free-electrons.com>\0" + "Subject\0Re: [PATCH 0/4] clk: mvebu: fix clk init order\0" "Date\0Tue, 18 Feb 2014 10:47:00 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" - "\00:1\0" + "To\0Ezequiel Garcia <ezequiel.garcia@free-electrons.com>" + " Emilio L\303\263pez <emilio@elopez.com.ar>\0" + "Cc\0Jason Cooper <jason@lakedaemon.net>" + Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> + Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + Andrew Lunn <andrew@lunn.ch> + Mike Turquette <mturquette@linaro.org> + linux-kernel@vger.kernel.org + " linux-arm-kernel@lists.infradead.org\0" + "\01:1\0" "b\0" "On 17/02/2014 19:19, Ezequiel Garcia wrote:\n" "> On Mon, Feb 17, 2014 at 04:59:01PM +0100, Gregory CLEMENT wrote:\n" @@ -107,13 +115,136 @@ "Gregory Clement, Free Electrons\n" "Kernel, drivers, real-time and embedded Linux\n" "development, consulting, training and support.\n" - "http://free-electrons.com\n" - "-------------- next part --------------\n" - "A non-text attachment was scrubbed...\n" - "Name: 0001-RFC-clk-mvebu-make-clock-output-names-mandatory.patch\n" - "Type: text/x-diff\n" - "Size: 4907 bytes\n" - "Desc: not available\n" - URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140218/aa2cea05/attachment.bin> + http://free-electrons.com + "\01:2\0" + "fn\00001-RFC-clk-mvebu-make-clock-output-names-mandatory.patch\0" + "b\0" + ">From ca82f66b8fbb8247b0ec2c407726105e1e1af419 Mon Sep 17 00:00:00 2001\n" + "From: Gregory CLEMENT <gregory.clement@free-electrons.com>\n" + "Date: Tue, 18 Feb 2014 10:38:08 +0100\n" + "Subject: [PATCH] [RFC] clk:mvebu: make clock-output-names mandatory\n" + "\n" + "Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>\n" + "---\n" + " .../devicetree/bindings/clock/mvebu-core-clock.txt | 7 ++--\n" + " arch/arm/boot/dts/armada-370.dtsi | 1 +\n" + " drivers/clk/mvebu/common.c | 38 +++++++++++++++-------\n" + " 3 files changed, 31 insertions(+), 15 deletions(-)\n" + "\n" + "diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt\n" + "index 307a503c5db8..4f2e3953b6a6 100644\n" + "--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt\n" + "+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt\n" + "@@ -40,16 +40,15 @@ Required properties:\n" + " \t\"marvell,mv88f6180-core-clock\" - for Kirkwood MV88f6180 SoC\n" + " - reg : shall be the register address of the Sample-At-Reset (SAR) register\n" + " - #clock-cells : from common clock binding; shall be set to 1\n" + "-\n" + "-Optional properties:\n" + "-- clock-output-names : from common clock binding; allows overwrite default clock\n" + "-\toutput names (\"tclk\", \"cpuclk\", \"l2clk\", \"ddrclk\")\n" + "+- clock-output-names : from common clock binding; should be the clock\n" + "+\toutput names given above\n" + " \n" + " Example:\n" + " \n" + " core_clk: core-clocks@d0214 {\n" + " \tcompatible = \"marvell,dove-core-clock\";\n" + " \treg = <0xd0214 0x4>;\n" + "+\tclock-output-names = \"tclk\", \"cpuclk\", \"l2clk\", \"ddrclk\";\n" + " \t#clock-cells = <1>;\n" + " };\n" + " \n" + "diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi\n" + "index af1f11e9e5a0..0d5853d05bd6 100644\n" + "--- a/arch/arm/boot/dts/armada-370.dtsi\n" + "+++ b/arch/arm/boot/dts/armada-370.dtsi\n" + "@@ -196,6 +196,7 @@\n" + " \t\t\tcoreclk: mvebu-sar@18230 {\n" + " \t\t\t\tcompatible = \"marvell,armada-370-core-clock\";\n" + " \t\t\t\treg = <0x18230 0x08>;\n" + "+\t\t\t\tclock-output-names = \"tclk\", \"cpuclk\", \"nbclk\", \"hclk\", \"dramclk\";\n" + " \t\t\t\t#clock-cells = <1>;\n" + " \t\t\t};\n" + " \n" + "diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c\n" + "index 25ceccf939ad..5e7c9274e4d3 100644\n" + "--- a/drivers/clk/mvebu/common.c\n" + "+++ b/drivers/clk/mvebu/common.c\n" + "@@ -51,16 +51,21 @@ void __init mvebu_coreclk_setup(struct device_node *np,\n" + " \t}\n" + " \n" + " \t/* Register TCLK */\n" + "-\tof_property_read_string_index(np, \"clock-output-names\", 0,\n" + "-\t\t\t\t &tclk_name);\n" + "+\tif (of_property_read_string_index(np, \"clock-output-names\", 0,\n" + "+\t\t\t\t\t\t&tclk_name))\n" + "+\t\tpr_err(\"%s[0]: clock-output-names is mandatory\\n\"\n" + "+\t\t\t\"\\\"%s\\\" will be used by default\\n\", np->name, tclk_name);\n" + " \trate = desc->get_tclk_freq(base);\n" + " \tclk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL,\n" + " \t\t\t\t\t\t CLK_IS_ROOT, rate);\n" + " \tWARN_ON(IS_ERR(clk_data.clks[0]));\n" + " \n" + " \t/* Register CPU clock */\n" + "-\tof_property_read_string_index(np, \"clock-output-names\", 1,\n" + "-\t\t\t\t &cpuclk_name);\n" + "+\tif (of_property_read_string_index(np, \"clock-output-names\", 1,\n" + "+\t\t\t\t\t\t&cpuclk_name))\n" + "+\t\tpr_err(\"%s[1]: clock-output-names is mandatory\\n\"\n" + "+\t\t\t\"\\\"%s\\\" will be used by default\\n\",\n" + "+\t\t\tnp->name, cpuclk_name);\n" + " \trate = desc->get_cpu_freq(base);\n" + " \tclk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL,\n" + " \t\t\t\t\t\t CLK_IS_ROOT, rate);\n" + "@@ -71,8 +76,11 @@ void __init mvebu_coreclk_setup(struct device_node *np,\n" + " \t\tconst char *rclk_name = desc->ratios[n].name;\n" + " \t\tint mult, div;\n" + " \n" + "-\t\tof_property_read_string_index(np, \"clock-output-names\",\n" + "-\t\t\t\t\t 2+n, &rclk_name);\n" + "+\t\tif (of_property_read_string_index(np, \"clock-output-names\",\n" + "+\t\t\t\t\t\t\t2+n, &rclk_name))\n" + "+\t\t\tpr_err(\"%s[%d]:clock-output-names is mandatory\\n\"\n" + "+\t\t\t\t\"\\\"%s\\\" will be used by default\\n\",\n" + "+\t\t\t\tnp->name, 2+n, rclk_name);\n" + " \t\tdesc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div);\n" + " \t\tclk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name,\n" + " \t\t\t\t cpuclk_name, 0, mult, div);\n" + "@@ -119,19 +127,27 @@ void __init mvebu_clk_gating_setup(struct device_node *np,\n" + " \t\t\t\t const struct clk_gating_soc_desc *desc)\n" + " {\n" + " \tstruct clk_gating_ctrl *ctrl;\n" + "-\tstruct clk *clk;\n" + " \tvoid __iomem *base;\n" + " \tconst char *default_parent = NULL;\n" + " \tint n;\n" + "+\tstruct of_phandle_args clkspec;\n" + " \n" + " \tbase = of_iomap(np, 0);\n" + " \tif (WARN_ON(!base))\n" + " \t\treturn;\n" + " \n" + "-\tclk = of_clk_get(np, 0);\n" + "-\tif (!IS_ERR(clk)) {\n" + "-\t\tdefault_parent = __clk_get_name(clk);\n" + "-\t\tclk_put(clk);\n" + "+\tif (!of_parse_phandle_with_args(np, \"clocks\", \"#clock-cells\", 0, &clkspec)) {\n" + "+\t\tof_property_read_string_index(clkspec.np, \"clock-output-names\",\n" + "+\t\t\t\t\tclkspec.args_count ? clkspec.args[0] : 0,\n" + "+\t\t\t\t\t&default_parent);\n" + "+\t\tif (WARN_ON(default_parent == NULL)) {\n" + "+\t\t\tpr_err(\"%s: The clock-output-names of the parent clock is mandatory.\\n\"\n" + "+\t\t\t\t\"%s: As this proprety is missing, this parent will be ignored.\\n\"\n" + "+\t\t\t\t\"%s: The tclk clock will be used as parent clock\\n\",\n" + "+\t\t\t\tnp->name, np->name, np->name);\n" + "+\t\t\tdefault_parent = \"tclk\";\n" + "+\t\t}\n" + "+\t\tof_node_put(clkspec.np);\n" + " \t}\n" + " \n" + " \tctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);\n" + "-- \n" + 1.8.1.2 -c6f6260886ac0b0613c7eff913cd278644aa9db6aa07b78a20e044a5fb9c383c +6e79adbcedd3ada46f4c2f5f1e73463a47c529959185ebdfa9ac7237016dd03c
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