From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: Bringing up sequence for non-boot CPU fails Date: Tue, 18 Feb 2014 18:33:48 +0000 Message-ID: <5303A78C.6090709@citrix.com> References: <1392725646.11080.47.camel@kazak.uk.xensource.com> <1392727989.11080.61.camel@kazak.uk.xensource.com> <1392730494.11080.62.camel@kazak.uk.xensource.com> <1392737632.23084.4.camel@kazak.uk.xensource.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Oleksandr Tyshchenko Cc: Ian Campbell , Andrii Anisov , "xen-devel@lists.xen.org" List-Id: xen-devel@lists.xenproject.org On 02/18/2014 06:17 PM, Oleksandr Tyshchenko wrote: > Ian, Hello Oleksandr, > I have checked your suggestion with full cache flush. > For this purposes I have used ARMV7 specific function from our U-Boot. > This function performs clean and invalidation of the entire data cache > at all levels. Did you try to only clean the cache? When page table for the secondary CPU is created Xen only clean the cache for the specific range. I suspect it's not enough and we need to invalidate. It should be easy to try with this small patch: diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index e00be9e..5a8aba2 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -234,7 +234,7 @@ static inline void clean_xen_dcache_va_range(void *p, unsigned long size) void *end; dsb(); /* So the CPU issues all writes to the range */ for ( end = p + size; p < end; p += cacheline_bytes ) - asm volatile (__clean_xen_dcache_one(0) : : "r" (p)); + asm volatile (__clean_and_invalidate_xen_dcache_one(0) : : "r" (p)); dsb(); /* So we know the flushes happen before continuing */ } Regards, -- Julien Grall