From: Stephen Warren <swarren@wwwdotorg.org>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3 2/3] usb: tegra: fix PHY configuration
Date: Tue, 18 Feb 2014 11:44:45 -0700 [thread overview]
Message-ID: <5303AA1D.6030005@wwwdotorg.org> (raw)
In-Reply-To: <b832da9b8f0e8ad1bd400d2ea0a3337646967bd4.1392579568.git.stefan@agner.ch>
On 02/16/2014 12:50 PM, Stefan Agner wrote:
> On Tegra30 and later, the PTS (parallel transceiver select) and STS
> (serial transceiver select) are part of the HOSTPC1_DEVLC_0 register
> rather than PORTSC1_0 register. Since the reset configuration
> usually matches the intended configuration, this error did not show
> up on Tegra30 devices.
>
> Also use the slightly different bit fields of first USB, (USBD) on
> Tegra20 and move those definitions to the Tegra20 specific header
> file.
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Hmm, the kernel has some potential bugs in this area as well:-( At
least, on Tegra20, phy-tegra-usb.c:set_pts() does the wrong thing on the
USB1 port. Luckily, the driver skips calling set_pts() on USB1, so this
isn't an actual issue.
next prev parent reply other threads:[~2014-02-18 18:44 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-16 19:50 [U-Boot] [PATCH v3 0/3] ubs: tegra: two fixes and cleanup Stefan Agner
2014-02-16 19:50 ` [U-Boot] [PATCH v3 1/3] usb: tegra: fix USB2 powerdown for Tegra30 and later Stefan Agner
2014-02-18 18:23 ` Stephen Warren
2014-02-16 19:50 ` [U-Boot] [PATCH v3 2/3] usb: tegra: fix PHY configuration Stefan Agner
2014-02-18 18:44 ` Stephen Warren [this message]
2014-02-16 19:50 ` [U-Boot] [PATCH v3 3/3] usb: tegra: combine header file Stefan Agner
2014-02-18 19:27 ` Stephen Warren
2014-02-18 22:20 ` Stefan Agner
2014-02-18 22:49 ` Stephen Warren
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