From: Santosh Shilimkar <santosh.shilimkar@ti.com>
To: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
grygorii.strashko@ti.com, linux@arm.linux.org.uk,
pawel.moll@arm.com, swarren@wwwdotorg.org,
gregkh@linuxfoundation.org, ijc+devicetree@hellion.org.uk,
nsekhar@ti.com, galak@kernel.crashing.org,
rob.herring@calxeda.com, linux-kernel@vger.kernel.org,
linux-mtd@lists.infradead.org, rob@landley.net,
dwmw2@infradead.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v5 2/2] memory: ti-aemif: add bindings for AEMIF driver
Date: Wed, 19 Feb 2014 09:13:19 -0500 [thread overview]
Message-ID: <5304BBFF.3070502@ti.com> (raw)
In-Reply-To: <1392817210-14312-3-git-send-email-ivan.khoronzhuk@ti.com>
On Wednesday 19 February 2014 08:40 AM, Ivan Khoronzhuk wrote:
> Add bindings for TI Async External Memory Interface (AEMIF) controller.
>
> The Async External Memory Interface (EMIF16/AEMIF) controller is intended to
> provide a glue-less interface to a variety of asynchronous memory devices like
> ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories
> can be accessed via 4 chip selects with 64M byte access per chip select.
>
> We are not encoding CS number in reg property, it's memory partition number.
> The CS number is encoded for Davinci NAND node using standalone property
> "ti,davinci-chipselect" and we need to provide two memory ranges to it,
> as result we can't encode CS number in "reg" for AEMIF child devices
> (NAND/NOR/etc), as it will break bindings compatibility.
>
> In this patch, NAND node is used just as an example of child node.
>
> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
> ---
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
WARNING: multiple messages have this Message-ID (diff)
From: santosh.shilimkar@ti.com (Santosh Shilimkar)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 2/2] memory: ti-aemif: add bindings for AEMIF driver
Date: Wed, 19 Feb 2014 09:13:19 -0500 [thread overview]
Message-ID: <5304BBFF.3070502@ti.com> (raw)
In-Reply-To: <1392817210-14312-3-git-send-email-ivan.khoronzhuk@ti.com>
On Wednesday 19 February 2014 08:40 AM, Ivan Khoronzhuk wrote:
> Add bindings for TI Async External Memory Interface (AEMIF) controller.
>
> The Async External Memory Interface (EMIF16/AEMIF) controller is intended to
> provide a glue-less interface to a variety of asynchronous memory devices like
> ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories
> can be accessed via 4 chip selects with 64M byte access per chip select.
>
> We are not encoding CS number in reg property, it's memory partition number.
> The CS number is encoded for Davinci NAND node using standalone property
> "ti,davinci-chipselect" and we need to provide two memory ranges to it,
> as result we can't encode CS number in "reg" for AEMIF child devices
> (NAND/NOR/etc), as it will break bindings compatibility.
>
> In this patch, NAND node is used just as an example of child node.
>
> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
> ---
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
WARNING: multiple messages have this Message-ID (diff)
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
To: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Cc: gregkh@linuxfoundation.org, galak@kernel.crashing.org,
rob@landley.net, linux@arm.linux.org.uk,
devicetree@vger.kernel.org, pawel.moll@arm.com,
mark.rutland@arm.com, rob.herring@calxeda.com,
swarren@wwwdotorg.org, ijc+devicetree@hellion.org.uk,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mtd@lists.infradead.org, grygorii.strashko@ti.com,
dwmw2@infradead.org, nsekhar@ti.com
Subject: Re: [PATCH v5 2/2] memory: ti-aemif: add bindings for AEMIF driver
Date: Wed, 19 Feb 2014 09:13:19 -0500 [thread overview]
Message-ID: <5304BBFF.3070502@ti.com> (raw)
In-Reply-To: <1392817210-14312-3-git-send-email-ivan.khoronzhuk@ti.com>
On Wednesday 19 February 2014 08:40 AM, Ivan Khoronzhuk wrote:
> Add bindings for TI Async External Memory Interface (AEMIF) controller.
>
> The Async External Memory Interface (EMIF16/AEMIF) controller is intended to
> provide a glue-less interface to a variety of asynchronous memory devices like
> ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories
> can be accessed via 4 chip selects with 64M byte access per chip select.
>
> We are not encoding CS number in reg property, it's memory partition number.
> The CS number is encoded for Davinci NAND node using standalone property
> "ti,davinci-chipselect" and we need to provide two memory ranges to it,
> as result we can't encode CS number in "reg" for AEMIF child devices
> (NAND/NOR/etc), as it will break bindings compatibility.
>
> In this patch, NAND node is used just as an example of child node.
>
> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
> ---
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
WARNING: multiple messages have this Message-ID (diff)
From: Santosh Shilimkar <santosh.shilimkar@ti.com>
To: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Cc: <gregkh@linuxfoundation.org>, <galak@kernel.crashing.org>,
<rob@landley.net>, <linux@arm.linux.org.uk>,
<devicetree@vger.kernel.org>, <pawel.moll@arm.com>,
<mark.rutland@arm.com>, <rob.herring@calxeda.com>,
<swarren@wwwdotorg.org>, <ijc+devicetree@hellion.org.uk>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mtd@lists.infradead.org>, <grygorii.strashko@ti.com>,
<dwmw2@infradead.org>, <nsekhar@ti.com>
Subject: Re: [PATCH v5 2/2] memory: ti-aemif: add bindings for AEMIF driver
Date: Wed, 19 Feb 2014 09:13:19 -0500 [thread overview]
Message-ID: <5304BBFF.3070502@ti.com> (raw)
In-Reply-To: <1392817210-14312-3-git-send-email-ivan.khoronzhuk@ti.com>
On Wednesday 19 February 2014 08:40 AM, Ivan Khoronzhuk wrote:
> Add bindings for TI Async External Memory Interface (AEMIF) controller.
>
> The Async External Memory Interface (EMIF16/AEMIF) controller is intended to
> provide a glue-less interface to a variety of asynchronous memory devices like
> ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories
> can be accessed via 4 chip selects with 64M byte access per chip select.
>
> We are not encoding CS number in reg property, it's memory partition number.
> The CS number is encoded for Davinci NAND node using standalone property
> "ti,davinci-chipselect" and we need to provide two memory ranges to it,
> as result we can't encode CS number in "reg" for AEMIF child devices
> (NAND/NOR/etc), as it will break bindings compatibility.
>
> In this patch, NAND node is used just as an example of child node.
>
> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
> ---
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
next prev parent reply other threads:[~2014-02-19 14:13 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-19 13:40 [PATCH v5 0/2] Introduce AEMIF driver for Davinci/Keystone archs Ivan Khoronzhuk
2014-02-19 13:40 ` Ivan Khoronzhuk
2014-02-19 13:40 ` Ivan Khoronzhuk
2014-02-19 13:40 ` Ivan Khoronzhuk
2014-02-19 13:40 ` [PATCH v5 1/2] memory: ti-aemif: introduce AEMIF driver Ivan Khoronzhuk
2014-02-19 13:40 ` Ivan Khoronzhuk
2014-02-19 13:40 ` Ivan Khoronzhuk
2014-02-19 13:40 ` Ivan Khoronzhuk
2014-02-19 13:40 ` [PATCH v5 2/2] memory: ti-aemif: add bindings for " Ivan Khoronzhuk
2014-02-19 13:40 ` Ivan Khoronzhuk
2014-02-19 13:40 ` Ivan Khoronzhuk
2014-02-19 13:40 ` Ivan Khoronzhuk
2014-02-19 14:13 ` Santosh Shilimkar [this message]
2014-02-19 14:13 ` Santosh Shilimkar
2014-02-19 14:13 ` Santosh Shilimkar
2014-02-19 14:13 ` Santosh Shilimkar
2014-02-19 18:11 ` Mark Rutland
2014-02-19 18:11 ` Mark Rutland
2014-02-19 18:11 ` Mark Rutland
2014-02-19 18:11 ` Mark Rutland
2014-02-20 12:44 ` Ivan Khoronzhuk
2014-02-20 12:44 ` Ivan Khoronzhuk
2014-02-20 12:44 ` Ivan Khoronzhuk
2014-02-20 12:44 ` Ivan Khoronzhuk
2014-02-20 13:44 ` Rob Herring
2014-02-20 13:44 ` Rob Herring
2014-02-20 13:44 ` Rob Herring
2014-02-20 15:49 ` Ivan Khoronzhuk
2014-02-20 15:49 ` Ivan Khoronzhuk
2014-02-20 15:49 ` Ivan Khoronzhuk
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