From: Dave Hansen <dave.hansen@intel.com>
To: Peter Zijlstra <peterz@infradead.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>,
linux-kernel@vger.kernel.org,
Frederic Weisbecker <fweisbec@gmail.com>,
Mike Galbraith <efault@gmx.de>, Paul Mackerras <paulus@samba.org>,
Stephane Eranian <eranian@google.com>,
Andi Kleen <ak@linux.intel.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Matt Fleming <matt.fleming@intel.com>
Subject: Re: [PATCH v1 03/11] perf: Allow for multiple ring buffers per event
Date: Wed, 19 Feb 2014 14:02:36 -0800 [thread overview]
Message-ID: <530529FC.6080704@intel.com> (raw)
In-Reply-To: <20140217143340.GR27965@twins.programming.kicks-ass.net>
On 02/17/2014 06:33 AM, Peter Zijlstra wrote:
> Then write the PERF_RECORD_DATA structure into the normal ring-buffer
> location; set data_offset to point to the first page boundary, data_size
> to 1mb.
>
> Then frob things such that perf_mmap_to_page() for the next 1mb of pages
> points to your buffer pages and wipe the page-table entries.
Wouldn't we have to teach a ton of code how to be IRQ safe for this to
work? Just step one: how do we go modifying page tables safely from an
interrupt? mm->page_table_lock is a plain non-irq spinlock.
next prev parent reply other threads:[~2014-02-19 22:02 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-06 10:50 [PATCH v1 00/11] perf: Add support for Intel Processor Trace Alexander Shishkin
2014-02-06 10:50 ` [PATCH v1 01/11] x86: Add Intel Processor Trace (INTEL_PT) cpu feature detection Alexander Shishkin
2014-02-06 10:50 ` [PATCH v1 02/11] perf: Abstract ring_buffer backing store operations Alexander Shishkin
2014-02-06 10:50 ` [PATCH v1 03/11] perf: Allow for multiple ring buffers per event Alexander Shishkin
2014-02-17 14:33 ` Peter Zijlstra
2014-02-18 2:36 ` Andi Kleen
2014-03-14 10:38 ` Peter Zijlstra
2014-03-14 14:10 ` Andi Kleen
2014-03-18 14:06 ` Alexander Shishkin
2014-02-19 22:02 ` Dave Hansen [this message]
2014-03-10 9:59 ` Alexander Shishkin
2014-03-10 17:24 ` Andi Kleen
2014-03-14 10:44 ` Peter Zijlstra
2014-03-14 14:13 ` Andi Kleen
2014-03-14 10:41 ` Peter Zijlstra
2014-05-07 15:26 ` Peter Zijlstra
2014-05-07 19:25 ` Ingo Molnar
2014-05-07 21:08 ` Andi Kleen
2014-05-07 21:22 ` Peter Zijlstra
2014-05-08 3:26 ` Alexander Shishkin
2014-05-08 4:05 ` Alexander Shishkin
2014-05-08 9:08 ` Alexander Shishkin
2014-05-08 12:34 ` Alexander Shishkin
2014-05-08 12:41 ` Peter Zijlstra
2014-05-08 12:46 ` Alexander Shishkin
2014-05-08 14:16 ` Peter Zijlstra
2014-02-06 10:50 ` [PATCH v1 04/11] itrace: Infrastructure for instruction flow tracing units Alexander Shishkin
2014-02-06 10:50 ` [PATCH v1 05/11] itrace: Add functionality to include traces in perf event samples Alexander Shishkin
2014-02-06 10:50 ` [PATCH v1 06/11] itrace: Add functionality to include traces in process core dumps Alexander Shishkin
2014-02-06 10:50 ` [PATCH v1 07/11] x86: perf: intel_pt: Intel PT PMU driver Alexander Shishkin
2014-02-06 20:29 ` Andi Kleen
2014-02-17 14:44 ` Peter Zijlstra
2014-02-17 16:07 ` Andi Kleen
2014-02-17 14:46 ` Peter Zijlstra
2014-02-18 12:42 ` Alexander Shishkin
2014-02-06 10:50 ` [PATCH v1 08/11] x86: perf: intel_pt: Add sampling functionality Alexander Shishkin
2014-02-06 10:50 ` [PATCH v1 09/11] x86: perf: intel_pt: Add core dump functionality Alexander Shishkin
2014-02-06 20:36 ` Andi Kleen
2014-02-07 9:03 ` Alexander Shishkin
2014-02-06 23:59 ` Andi Kleen
2014-02-07 9:09 ` Alexander Shishkin
2014-02-06 10:50 ` [PATCH v1 10/11] x86: perf: intel_bts: Add BTS PMU driver Alexander Shishkin
2014-02-06 10:50 ` [PATCH v1 11/11] x86: perf: intel_bts: Add core dump related functionality Alexander Shishkin
2014-02-06 23:57 ` Andi Kleen
2014-02-07 9:02 ` Alexander Shishkin
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