Re: [Xenomai] xenomai , irq and pci

[Johann Obermayr <johann.obermayr@sigmatek.at>]

Am 05.03.2014 20:59, schrieb Jeroen Van den Keybus:
>
>     >> task0 is one high prior in primary domain on core0.
>     >> this task wait for event, that is fired by fpga irq.
>     >> than this task will make some pci accesses to the fpga.
>
>
> A while ago (11/02) you wrote to this list ('[Xenomai] Xenomai and pci 
> access') because you had issues with PCI transfers. Did you fix those 
> ? How large are your transfers ?
The old part we have fixed. (but not very beautyful). But it work.

Our write transfer has 10kByte, and this need 1,8 ms. And our system 
work with
1ms ticks. That  mean , our rt-task will start every 1ms.

>
>     >> the other task (task1) is a shadow task, but running in
>     secondary domain
>     >> on core 1.
>     >> This task make many big memcpy to sram.
>
>
> I remember having asked for the complete PCI bus layout and to try out 
> other memory access methods besides memcpy. Did this do anything ?
>
We can't change the memcpy function.

> Since you mention you have an FPGA, I would now suggest instrumenting 
> it (add some logging) as to find out when and how (regular intervals 
> or with interruptions) your FPGA is accessed by the PCI bus.
>
Now we will measure all available hardware points.
FPGA output, PCI bus, PCIe ??,  and than the interrupt line to the core.