From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [PATCH v3 2/3] KVM: nVMX: Fully emulate preemption timer Date: Fri, 07 Mar 2014 18:24:26 +0100 Message-ID: <531A00CA.80504@redhat.com> References: <20140307172035.GA30738@amt.cnet> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Cc: Gleb Natapov , kvm To: Marcelo Tosatti , Jan Kiszka Return-path: Received: from mx1.redhat.com ([209.132.183.28]:26213 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751688AbaCGRYd (ORCPT ); Fri, 7 Mar 2014 12:24:33 -0500 In-Reply-To: <20140307172035.GA30738@amt.cnet> Sender: kvm-owner@vger.kernel.org List-ID: Il 07/03/2014 18:20, Marcelo Tosatti ha scritto: > On Thu, Mar 06, 2014 at 06:33:58PM +0100, Jan Kiszka wrote: >> > We cannot rely on the hardware-provided preemption timer support because >> > we are holding L2 in HLT outside non-root mode. >> > Furthermore, emulating >> > the preemption will resolve tick rate errata on older Intel CPUs. > Can you describe this in more detail please? Errata number? AAT59 and AAK139. Basically the rate of the preemption timer is wrong and unpredictable. http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-5500-specification-update.pdf http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/core-mobile-spec-update.pdf Paolo