From mboxrd@z Thu Jan  1 00:00:00 1970
From: York Sun <yorksun@freescale.com>
Date: Fri, 7 Mar 2014 11:37:52 -0800
Subject: [U-Boot] [PATCH] board/b4860qds:Slow MDC clock to comply IEEE
 specs in PBI config
In-Reply-To: <1393577339-4541-1-git-send-email-prabhakar@freescale.com>
References: <1393577339-4541-1-git-send-email-prabhakar@freescale.com>
Message-ID: <531A2010.9040806@freescale.com>
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On 02/28/2014 12:48 AM, Prabhakar Kushwaha wrote:
> With the default value of MDIO_CLK_DIV generatee MDC is too high and It is
> violating the IEEE specs much higher than 2.5Mhz.
> 
> Although there is errata(A-006260) for EMI2(MDIO2), but same errata is
> been hit on EMI1(MDIO1). unfortunately this errata never hit on B4 rev1.
> So reduced the MDIO_CLK_DIV value.
> 

Please fix the typo and some grammar error in the commit message.
What is about B4 Rev 1? We support rev 2 and later in this u-boot.

York