[U-Boot] [PATCH v3] powerpc/t2080rdb: Add T2080PCIe-RDB board support

[York Sun <yorksun@freescale.com>]

On 03/04/2014 11:04 PM, Shengzhou Liu wrote:
> T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
> It works in two mode: standalone mode and PCIe endpoint mode.
> 
> T2080PCIe-RDB Feature Overview
> ------------------------------
> Processor:
>  - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
> DDR Memory:
>  - Single memory controller capable of supporting DDR3 and DDR3-LP devices
>  - 72bit 4GB DDR3-LP SODIMM in slot
> Ethernet interfaces:
>  - Two 10M/100M/1G RGMII ports on-board
>  - Two 10Gbps SFP+ ports on-board
>  - Two 10Gbps Base-T ports on-board
> Accelerator:
>  - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
> SerDes 16 lanes configuration:
>  - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
>  - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
>  - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
>  - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
>  - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
>  - SerDes-2 Lane G-H: to SATA1 & SATA2
> IFC/Local Bus:
>  - NOR:  128MB 16-bit NOR flash
>  - NAND: 512MB 8-bit NAND flash
>  - CPLD: for system controlling with programable header on-board
> eSPI:
>  - 64MB N25Q512 SPI flash
> USB:
>  - Two USB2.0 ports with internal PHY (both Type-A)
> PCIe:
>  - One PCIe x4 gold-finger
>  - One PCIe x4 connector
>  - One PCIe x2 end-point device (C293 Crypto co-processor)
> SATA:
>  - Two SATA 2.0 ports on-board
> SDHC:
>  - support a TF-card on-board
> I2C:
>  - Four I2C controllers.
> UART:
>  - Dual 4-pins UART serial ports
> 
> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
> ---
> v3: rename PHY address to match Cortina PHY driver.
> v2: updated readme.
>

Applied to u-boot-mpc85xx/master. Thanks.

York