From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51258) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WMlkz-0003Ib-Dq for qemu-devel@nongnu.org; Sun, 09 Mar 2014 17:59:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WMlku-0001LJ-TQ for qemu-devel@nongnu.org; Sun, 09 Mar 2014 17:59:41 -0400 Received: from s16892447.onlinehome-server.info ([82.165.15.123]:59958) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WMlku-0001K0-OK for qemu-devel@nongnu.org; Sun, 09 Mar 2014 17:59:36 -0400 Message-ID: <531CE3B2.5040302@ilande.co.uk> Date: Sun, 09 Mar 2014 21:57:06 +0000 From: Mark Cave-Ayland MIME-Version: 1.0 References: <531C4A43.1030309@embedded-brains.de> In-Reply-To: <531C4A43.1030309@embedded-brains.de> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH v5] target-sparc: Add and use CPU_FEATURE_CASA List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Sebastian Huber Cc: blauwirbel@gmail.com, rth@twiddle.net, qemu-devel@nongnu.org, Fabien Chouteau , afaerber@suse.de On 09/03/14 11:02, Sebastian Huber wrote: > The LEON3 processor has support for the CASA instruction which is > normally only available for SPARC V9 processors. Binutils 2.24 > and GCC 4.9 will support this instruction for LEON3. GCC uses it to > generate C11 atomic operations. > > The CAS synthetic instruction uses an ASI of 0x80. If TARGET_SPARC64 is > not defined use a supervisor data load/store for an ASI of 0x80 in > helper_ld_asi()/helper_st_asi(). The supervisor data load/store was > choosen according to the LEON3 documentation. > > The ASI 0x80 is defined in the SPARC V9 manual, Table 12—Address Space > Identifiers (ASIs). Here we have: 0x80, ASI_PRIMARY, Unrestricted > access, Primary address space. > > Tested with the following program: > > #include > #include > > void test(void) > { > atomic_int a; > int e; > _Bool b; > > atomic_store(&a, 1); > e = 1; > b = atomic_compare_exchange_strong(&a, &e, 2); > assert(b); > assert(atomic_load(&a) == 2); > > atomic_store(&a, 3); > e = 4; > b = atomic_compare_exchange_strong(&a, &e, 5); > assert(!b); > assert(atomic_load(&a) == 3); > } > > Tested also on a NGMP board with a LEON4 processor. > > Reviewed-by: Fabien Chouteau > Reviewed-by: Andreas Färber > Signed-off-by: Sebastian Huber > > v4: Fix coding style. > > v5: Fix two typos. Generate an IU instead of FPU exception in case CASA > is not supported by the CPU. Define CASA feature for all SPARC64 CPUs > (due to the #ifndef TARGET_SPARC64 it must go into the #else branch). This version of the patch passes all of my tests on SPARC32 and SPARC64 so: Tested-by: Mark Cave-Ayland If someone like Richard (added as CC) could give the TCG parts a quick sanity check then given the length of time this patch has been around (and Sebastian's responsiveness) then I'd be okay for this patch to be included in 2.0. ATB, Mark.