From: Tomasz Figa <t.figa@samsung.com>
To: Sachin Kamat <sachin.kamat@linaro.org>,
linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org, mturquette@linaro.org
Subject: Re: [PATCH 1/1] clk: exynos-5420: Fix VPLL lock offset
Date: Thu, 13 Mar 2014 12:53:00 +0100 [thread overview]
Message-ID: <53219C1C.1030501@samsung.com> (raw)
In-Reply-To: <1394681222-27882-1-git-send-email-sachin.kamat@linaro.org>
Hi Sachin,
On 13.03.2014 04:27, Sachin Kamat wrote:
> Set it as per the user manual.
>
> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> ---
> drivers/clk/samsung/clk-exynos5420.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 60b26819bed5..7fd6bea467fd 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -33,7 +33,7 @@
> #define RPLL_LOCK 0x10050
> #define IPLL_LOCK 0x10060
> #define SPLL_LOCK 0x10070
> -#define VPLL_LOCK 0x10070
> +#define VPLL_LOCK 0x10080
> #define MPLL_LOCK 0x10090
> #define CPLL_CON0 0x10120
> #define DPLL_CON0 0x10128
>
Looks fine. Will queue for 3.15, since ATM there is no support for PLL
rate setting on Exynos 5420 (no rate tables registered).
Best regards,
Tomasz
WARNING: multiple messages have this Message-ID (diff)
From: t.figa@samsung.com (Tomasz Figa)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/1] clk: exynos-5420: Fix VPLL lock offset
Date: Thu, 13 Mar 2014 12:53:00 +0100 [thread overview]
Message-ID: <53219C1C.1030501@samsung.com> (raw)
In-Reply-To: <1394681222-27882-1-git-send-email-sachin.kamat@linaro.org>
Hi Sachin,
On 13.03.2014 04:27, Sachin Kamat wrote:
> Set it as per the user manual.
>
> Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
> ---
> drivers/clk/samsung/clk-exynos5420.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 60b26819bed5..7fd6bea467fd 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -33,7 +33,7 @@
> #define RPLL_LOCK 0x10050
> #define IPLL_LOCK 0x10060
> #define SPLL_LOCK 0x10070
> -#define VPLL_LOCK 0x10070
> +#define VPLL_LOCK 0x10080
> #define MPLL_LOCK 0x10090
> #define CPLL_CON0 0x10120
> #define DPLL_CON0 0x10128
>
Looks fine. Will queue for 3.15, since ATM there is no support for PLL
rate setting on Exynos 5420 (no rate tables registered).
Best regards,
Tomasz
next prev parent reply other threads:[~2014-03-13 11:53 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-13 3:27 [PATCH 1/1] clk: exynos-5420: Fix VPLL lock offset Sachin Kamat
2014-03-13 3:27 ` Sachin Kamat
2014-03-13 11:53 ` Tomasz Figa [this message]
2014-03-13 11:53 ` Tomasz Figa
2014-03-13 14:57 ` Sachin Kamat
2014-03-13 14:57 ` Sachin Kamat
2014-05-01 11:10 ` Sachin Kamat
2014-05-01 11:10 ` Sachin Kamat
2014-05-01 17:19 ` Tomasz Figa
2014-05-01 17:19 ` Tomasz Figa
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=53219C1C.1030501@samsung.com \
--to=t.figa@samsung.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-samsung-soc@vger.kernel.org \
--cc=mturquette@linaro.org \
--cc=sachin.kamat@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.