From: Tomasz Figa <tomasz.figa@gmail.com>
To: armdev <armdev.ftm@gmail.com>, Tushar Behera <tushar.behera@linaro.org>
Cc: linux-samsung-soc <linux-samsung-soc@vger.kernel.org>,
u-boot@lists.denx.de
Subject: Re: Enabling uart 3 in arndale
Date: Sun, 16 Mar 2014 13:53:09 +0100 [thread overview]
Message-ID: <53259EB5.8090202@gmail.com> (raw)
In-Reply-To: <0259D8EA-B62C-4D07-8661-ED2CF6E53779@gmail.com>
Hi,
On 14.03.2014 09:04, armdev wrote:
> Hi,
>
> We are trying to enable the UART3 on COM18 pins of arndale board. The UART3 RXD and TXD are on pins 2 and 4 which as per the base board specification is connected as
>
> XuRXD3 : UART_3_RXD/GPA1[4] : 2
> XuTXD3 : UART_3_TXD/GPA1[5] : 4
>
> As per the public reference manual of exynos 5250, there is a register GPACON (0x1140_0000)
> Setting GPACON |= 0x0010_0000 should enable the pins, but I am not able to see any output on UART3.
>
> Can you please suggest what is the right procedure
The register is GPA1CON and its GPA1CON[4] and [5] bit fields need both
to be set to 0x2 - see Pad Control chapter of Exynos5250 public
datasheet. Also GPA1PUD should be reconfigured to disable default
pull-down on both pins, again you can find details of the register in
the datasheet.
Best regards,
Tomasz
WARNING: multiple messages have this Message-ID (diff)
From: Tomasz Figa <tomasz.figa@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] Enabling uart 3 in arndale
Date: Sun, 16 Mar 2014 13:53:09 +0100 [thread overview]
Message-ID: <53259EB5.8090202@gmail.com> (raw)
In-Reply-To: <0259D8EA-B62C-4D07-8661-ED2CF6E53779@gmail.com>
Hi,
On 14.03.2014 09:04, armdev wrote:
> Hi,
>
> We are trying to enable the UART3 on COM18 pins of arndale board. The UART3 RXD and TXD are on pins 2 and 4 which as per the base board specification is connected as
>
> XuRXD3 : UART_3_RXD/GPA1[4] : 2
> XuTXD3 : UART_3_TXD/GPA1[5] : 4
>
> As per the public reference manual of exynos 5250, there is a register GPACON (0x1140_0000)
> Setting GPACON |= 0x0010_0000 should enable the pins, but I am not able to see any output on UART3.
>
> Can you please suggest what is the right procedure
The register is GPA1CON and its GPA1CON[4] and [5] bit fields need both
to be set to 0x2 - see Pad Control chapter of Exynos5250 public
datasheet. Also GPA1PUD should be reconfigured to disable default
pull-down on both pins, again you can find details of the register in
the datasheet.
Best regards,
Tomasz
next prev parent reply other threads:[~2014-03-16 12:53 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-14 8:04 Enabling uart 3 in arndale armdev
2014-03-14 8:04 ` [U-Boot] " armdev
2014-03-16 9:22 ` armdev
2014-03-16 9:22 ` [U-Boot] " armdev
2014-03-16 9:26 ` Michael Trimarchi
2014-03-16 9:26 ` Michael Trimarchi
2014-03-16 10:07 ` armdev
2014-03-16 10:07 ` armdev
2014-03-16 10:25 ` Michael Trimarchi
2014-03-16 10:25 ` Michael Trimarchi
2014-03-16 10:42 ` armdev
2014-03-16 10:42 ` armdev
2014-03-16 12:40 ` Tomasz Figa
2014-03-16 12:40 ` Tomasz Figa
2014-03-16 12:53 ` Tomasz Figa [this message]
2014-03-16 12:53 ` Tomasz Figa
2014-03-28 9:42 ` armdev
2014-03-28 9:42 ` [U-Boot] " armdev
2014-03-31 3:47 ` armdev
2014-03-31 3:47 ` [U-Boot] " armdev
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