diff for duplicates of <532714AE.2040206@gmail.com> diff --git a/a/1.txt b/N1/1.txt index 90ba1de..432b596 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,9 +1,9 @@ -On 03/17/2014 04:06 PM, Antoine T?nart wrote: +On 03/17/2014 04:06 PM, Antoine Ténart wrote: > Adds initial support for the Marvell Armada 1500 pro (BG2Q) SoC (Berlin family). > The SoC has nodes for cpu, l2 cache controller, interrupt controllers, local > timer, apb timers and uarts for now. > -> Signed-off-by: Antoine T?nart <antoine.tenart@free-electrons.com> +> Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> > Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> > --- > arch/arm/boot/dts/berlin2q.dtsi | 210 ++++++++++++++++++++++++++++++++++++++++ @@ -57,27 +57,27 @@ sorry I missed it the first time. Please add: > + ranges = <0 0xf7000000 0x1000000>; > + interrupt-parent = <&gic>; > + -> + l2: l2-cache-controller at ac0000 { +> + l2: l2-cache-controller@ac0000 { > + compatible = "arm,pl310-cache"; > + reg = <0xac0000 0x1000>; > + cache-level = <2>; > + }; > + -> + local-timer at ad0600 { +> + local-timer@ad0600 { > + compatible = "arm,cortex-a9-twd-timer"; > + reg = <0xad0600 0x20>; > + clocks = <&sysclk>; > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; > + }; > + -> + gic: interrupt-controller at ad1000 { +> + gic: interrupt-controller@ad1000 { > + compatible = "arm,cortex-a9-gic"; > + reg = <0xad1000 0x1000>, <0xad0100 0x100>; > + interrupt-controller; > + #interrupt-cells = <3>; > + }; > + -> + apb at e80000 { +> + apb@e80000 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; @@ -85,7 +85,7 @@ sorry I missed it the first time. Please add: > + ranges = <0 0xe80000 0x10000>; > + interrupt-parent = <&aic>; > + -> + timer0: timer at 2c00 { +> + timer0: timer@2c00 { > + compatible = "snps,dw-apb-timer"; > + reg = <0x2c00 0x14>; > + interrupts = <8>; @@ -97,49 +97,49 @@ clocks = <&cfgclk>; > + }; > + -> + timer1: timer at 2c14 { +> + timer1: timer@2c14 { > + compatible = "snps,dw-apb-timer"; > + reg = <0x2c14 0x14>; > + clock-freq = <100000000>; > + status = "disabled"; > + }; > + -> + timer2: timer at 2c28 { +> + timer2: timer@2c28 { > + compatible = "snps,dw-apb-timer"; > + reg = <0x2c28 0x14>; > + clock-freq = <100000000>; > + status = "disabled"; > + }; > + -> + timer3: timer at 2c3c { +> + timer3: timer@2c3c { > + compatible = "snps,dw-apb-timer"; > + reg = <0x2c3c 0x14>; > + clock-freq = <100000000>; > + status = "disabled"; > + }; > + -> + timer4: timer at 2c50 { +> + timer4: timer@2c50 { > + compatible = "snps,dw-apb-timer"; > + reg = <0x2c50 0x14>; > + clock-freq = <100000000>; > + status = "disabled"; > + }; > + -> + timer5: timer at 2c64 { +> + timer5: timer@2c64 { > + compatible = "snps,dw-apb-timer"; > + reg = <0x2c64 0x14>; > + clock-freq = <100000000>; > + status = "disabled"; > + }; > + -> + timer6: timer at 2c78 { +> + timer6: timer@2c78 { > + compatible = "snps,dw-apb-timer"; > + reg = <0x2c78 0x14>; > + clock-freq = <100000000>; > + status = "disabled"; > + }; > + -> + timer7: timer at 2c8c { +> + timer7: timer@2c8c { > + compatible = "snps,dw-apb-timer"; > + reg = <0x2c8c 0x14>; > + clock-freq = <100000000>; @@ -148,7 +148,7 @@ clocks = <&cfgclk>; > + [...] > + -> + uart0: uart at 9000 { +> + uart0: uart@9000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x9000 0x100>; > + interrupt-parent = <&sic>; @@ -161,7 +161,7 @@ and clocks = <&smclk> here and below. > + status = "disabled"; > + }; > + -> + uart1: uart at a000 { +> + uart1: uart@a000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0xa000 0x100>; > + interrupt-parent = <&sic>; diff --git a/a/content_digest b/N1/content_digest index 9b4df34..b665a93 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,17 +1,22 @@ "ref\01395068788-19786-1-git-send-email-antoine.tenart@free-electrons.com\0" "ref\01395068788-19786-2-git-send-email-antoine.tenart@free-electrons.com\0" - "From\0sebastian.hesselbarth@gmail.com (Sebastian Hesselbarth)\0" - "Subject\0[PATCH v3 1/3] ARM: dts: berlin2q: add the Marvell Armada 1500 pro\0" + "From\0Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>\0" + "Subject\0Re: [PATCH v3 1/3] ARM: dts: berlin2q: add the Marvell Armada 1500 pro\0" "Date\0Mon, 17 Mar 2014 16:28:46 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Antoine T\303\251nart <antoine.tenart@free-electrons.com>\0" + "Cc\0alexandre.belloni@free-electrons.com" + zmxu@marvell.com + jszhang@marvell.com + linux-arm-kernel@lists.infradead.org + " linux-kernel@vger.kernel.org\0" "\00:1\0" "b\0" - "On 03/17/2014 04:06 PM, Antoine T?nart wrote:\n" + "On 03/17/2014 04:06 PM, Antoine T\303\251nart wrote:\n" "> Adds initial support for the Marvell Armada 1500 pro (BG2Q) SoC (Berlin family).\n" "> The SoC has nodes for cpu, l2 cache controller, interrupt controllers, local\n" "> timer, apb timers and uarts for now.\n" ">\n" - "> Signed-off-by: Antoine T?nart <antoine.tenart@free-electrons.com>\n" + "> Signed-off-by: Antoine T\303\251nart <antoine.tenart@free-electrons.com>\n" "> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>\n" "> ---\n" "> arch/arm/boot/dts/berlin2q.dtsi | 210 ++++++++++++++++++++++++++++++++++++++++\n" @@ -65,27 +70,27 @@ "> +\t\tranges = <0 0xf7000000 0x1000000>;\n" "> +\t\tinterrupt-parent = <&gic>;\n" "> +\n" - "> +\t\tl2: l2-cache-controller at ac0000 {\n" + "> +\t\tl2: l2-cache-controller@ac0000 {\n" "> +\t\t\tcompatible = \"arm,pl310-cache\";\n" "> +\t\t\treg = <0xac0000 0x1000>;\n" "> +\t\t\tcache-level = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tlocal-timer at ad0600 {\n" + "> +\t\tlocal-timer@ad0600 {\n" "> +\t\t\tcompatible = \"arm,cortex-a9-twd-timer\";\n" "> +\t\t\treg = <0xad0600 0x20>;\n" "> +\t\t\tclocks = <&sysclk>;\n" "> +\t\t\tinterrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tgic: interrupt-controller at ad1000 {\n" + "> +\t\tgic: interrupt-controller@ad1000 {\n" "> +\t\t\tcompatible = \"arm,cortex-a9-gic\";\n" "> +\t\t\treg = <0xad1000 0x1000>, <0xad0100 0x100>;\n" "> +\t\t\tinterrupt-controller;\n" "> +\t\t\t#interrupt-cells = <3>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tapb at e80000 {\n" + "> +\t\tapb@e80000 {\n" "> +\t\t\tcompatible = \"simple-bus\";\n" "> +\t\t\t#address-cells = <1>;\n" "> +\t\t\t#size-cells = <1>;\n" @@ -93,7 +98,7 @@ "> +\t\t\tranges = <0 0xe80000 0x10000>;\n" "> +\t\t\tinterrupt-parent = <&aic>;\n" "> +\n" - "> +\t\t\ttimer0: timer at 2c00 {\n" + "> +\t\t\ttimer0: timer@2c00 {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-timer\";\n" "> +\t\t\t\treg = <0x2c00 0x14>;\n" "> +\t\t\t\tinterrupts = <8>;\n" @@ -105,49 +110,49 @@ "\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ttimer1: timer at 2c14 {\n" + "> +\t\t\ttimer1: timer@2c14 {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-timer\";\n" "> +\t\t\t\treg = <0x2c14 0x14>;\n" "> +\t\t\t\tclock-freq = <100000000>;\n" "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ttimer2: timer at 2c28 {\n" + "> +\t\t\ttimer2: timer@2c28 {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-timer\";\n" "> +\t\t\t\treg = <0x2c28 0x14>;\n" "> +\t\t\t\tclock-freq = <100000000>;\n" "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ttimer3: timer at 2c3c {\n" + "> +\t\t\ttimer3: timer@2c3c {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-timer\";\n" "> +\t\t\t\treg = <0x2c3c 0x14>;\n" "> +\t\t\t\tclock-freq = <100000000>;\n" "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ttimer4: timer at 2c50 {\n" + "> +\t\t\ttimer4: timer@2c50 {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-timer\";\n" "> +\t\t\t\treg = <0x2c50 0x14>;\n" "> +\t\t\t\tclock-freq = <100000000>;\n" "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ttimer5: timer at 2c64 {\n" + "> +\t\t\ttimer5: timer@2c64 {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-timer\";\n" "> +\t\t\t\treg = <0x2c64 0x14>;\n" "> +\t\t\t\tclock-freq = <100000000>;\n" "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ttimer6: timer at 2c78 {\n" + "> +\t\t\ttimer6: timer@2c78 {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-timer\";\n" "> +\t\t\t\treg = <0x2c78 0x14>;\n" "> +\t\t\t\tclock-freq = <100000000>;\n" "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\ttimer7: timer at 2c8c {\n" + "> +\t\t\ttimer7: timer@2c8c {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-timer\";\n" "> +\t\t\t\treg = <0x2c8c 0x14>;\n" "> +\t\t\t\tclock-freq = <100000000>;\n" @@ -156,7 +161,7 @@ "> +\n" "[...]\n" "> +\n" - "> +\t\t\tuart0: uart at 9000 {\n" + "> +\t\t\tuart0: uart@9000 {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\t\treg = <0x9000 0x100>;\n" "> +\t\t\t\tinterrupt-parent = <&sic>;\n" @@ -169,7 +174,7 @@ "> +\t\t\t\tstatus = \"disabled\";\n" "> +\t\t\t};\n" "> +\n" - "> +\t\t\tuart1: uart at a000 {\n" + "> +\t\t\tuart1: uart@a000 {\n" "> +\t\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\t\t\treg = <0xa000 0x100>;\n" "> +\t\t\t\tinterrupt-parent = <&sic>;\n" @@ -184,4 +189,4 @@ "\n" Sebastian -5aa34ae1721b737336ab273458570d79ae820a2f11a61686d9268bbdb94c3526 +dd6ae9e27edee15c9be073df8a5d8d713038a2d29eeaba27053f803916e57a11
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