From: Richard Henderson <rth@twiddle.net>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: "Peter Crosthwaite" <peter.crosthwaite@xilinx.com>,
patches@linaro.org, "Michael Matz" <matz@suse.de>,
"Alexander Graf" <agraf@suse.de>,
"Will Newton" <will.newton@linaro.org>,
"Dirk Mueller" <dmueller@suse.de>,
"Laurent Desnogues" <laurent.desnogues@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
kvmarm@lists.cs.columbia.edu,
"Christoffer Dall" <christoffer.dall@linaro.org>
Subject: Re: [Qemu-devel] [PATCH for-2.0 2/2] target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD)
Date: Tue, 18 Mar 2014 14:10:35 -0700 [thread overview]
Message-ID: <5328B64B.9050404@twiddle.net> (raw)
In-Reply-To: <1395170635-21281-3-git-send-email-peter.maydell@linaro.org>
On 03/18/2014 12:23 PM, Peter Maydell wrote:
> +#define USATACC(bits, shift) \
> + do { \
> + va = (int##bits##_t)((a >> shift) & ((1 << bits) - 1)); \
> + vb = (uint##bits##_t)((b >> shift) & ((1 << bits) - 1)); \
The masking seems redundant with the cast.
Perhaps better to use extract32/sextract32?
> + r |= (uint32_t) (vr & ((1 << bits) - 1)) << shift; \
Perhaps better with deposit32? That implies an unnecessary mask of R, but
perhaps the compiler can clean that up...
Otherwise I don't actually see anything wrong,
Reviewed-by: Richard Henderson <rth@twiddle.net>
r~
next prev parent reply other threads:[~2014-03-18 21:10 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-18 19:23 [Qemu-devel] [PATCH for-2.0 0/2] A64: Implement last four Neon insns Peter Maydell
2014-03-18 19:23 ` [Qemu-devel] [PATCH for-2.0 1/2] target-arm: A64: Add saturating int ops (SQNEG/SQABS) Peter Maydell
2014-03-18 20:51 ` Richard Henderson
2014-03-18 19:23 ` [Qemu-devel] [PATCH for-2.0 2/2] target-arm: A64: Add saturating accumulate ops (USQADD/SUQADD) Peter Maydell
2014-03-18 21:10 ` Richard Henderson [this message]
2014-03-18 22:42 ` Peter Maydell
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