From: antoine.tenart@free-electrons.com (Antoine Ténart)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/2] ARM: berlin: add scu and chipctrl device nodes for BG2/BG2Q
Date: Fri, 21 Mar 2014 10:20:24 +0100 [thread overview]
Message-ID: <532C0458.1090906@free-electrons.com> (raw)
In-Reply-To: <1395347986-30203-2-git-send-email-sebastian.hesselbarth@gmail.com>
On 20/03/2014 21:39, Sebastian Hesselbarth wrote:
> This adds scu and general purpose registers device nodes required for
> SMP on Berlin BG2 and BG2Q SoCs. The secondary CPUs will pick their jump
> address from general purpose (SW generic) register 1.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Antoine T?nart <antoine.tenart@free-electrons.com>
Also tested on the BG2Q,
Tested-by: Antoine T?nart <antoine.tenart@free-electrons.com>
> ---
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Pawel Moll <pawel.moll@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
> Cc: Kumar Gala <galak@codeaurora.org>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Antoine Tenart <antoine.tenart@free-electrons.com>
> Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> Cc: devicetree at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-kernel at vger.kernel.org
> ---
> arch/arm/boot/dts/berlin2.dtsi | 10 ++++++++++
> arch/arm/boot/dts/berlin2q.dtsi | 10 ++++++++++
> 2 files changed, 20 insertions(+)
>
> diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
> index 56a1af2f1052..4d85312dc17a 100644
> --- a/arch/arm/boot/dts/berlin2.dtsi
> +++ b/arch/arm/boot/dts/berlin2.dtsi
> @@ -72,6 +72,11 @@
> cache-level = <2>;
> };
>
> + scu: snoop-control-unit at ad0000 {
> + compatible = "arm,cortex-a9-scu";
> + reg = <0xad0000 0x58>;
> + };
> +
> gic: interrupt-controller at ad1000 {
> compatible = "arm,cortex-a9-gic";
> reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
> @@ -176,6 +181,11 @@
> };
> };
>
> + generic-regs at ea0184 {
> + compatible = "marvell,berlin-generic-regs", "syscon";
> + reg = <0xea0184 0x10>;
> + };
> +
> apb at fc0000 {
> compatible = "simple-bus";
> #address-cells = <1>;
> diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
> index 07452a7483fa..86d8a2c49f38 100644
> --- a/arch/arm/boot/dts/berlin2q.dtsi
> +++ b/arch/arm/boot/dts/berlin2q.dtsi
> @@ -87,6 +87,11 @@
> cache-level = <2>;
> };
>
> + scu: snoop-control-unit at ad0000 {
> + compatible = "arm,cortex-a9-scu";
> + reg = <0xad0000 0x58>;
> + };
> +
> local-timer at ad0600 {
> compatible = "arm,cortex-a9-twd-timer";
> reg = <0xad0600 0x20>;
> @@ -183,6 +188,11 @@
> };
> };
>
> + generic-regs at ea0110 {
> + compatible = "marvell,berlin-generic-regs", "syscon";
> + reg = <0xea0110 0x10>;
> + };
> +
> apb at fc0000 {
> compatible = "simple-bus";
> #address-cells = <1>;
>
--
Antoine T?nart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
WARNING: multiple messages have this Message-ID (diff)
From: "Antoine Ténart" <antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
To: Sebastian Hesselbarth
<sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Ian Campbell
<ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>,
Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>,
Alexandre Belloni
<alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH 1/2] ARM: berlin: add scu and chipctrl device nodes for BG2/BG2Q
Date: Fri, 21 Mar 2014 10:20:24 +0100 [thread overview]
Message-ID: <532C0458.1090906@free-electrons.com> (raw)
In-Reply-To: <1395347986-30203-2-git-send-email-sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On 20/03/2014 21:39, Sebastian Hesselbarth wrote:
> This adds scu and general purpose registers device nodes required for
> SMP on Berlin BG2 and BG2Q SoCs. The secondary CPUs will pick their jump
> address from general purpose (SW generic) register 1.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Acked-by: Antoine Ténart <antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Also tested on the BG2Q,
Tested-by: Antoine Ténart <antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> ---
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
> Cc: Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> Cc: Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
> Cc: Antoine Tenart <antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> Cc: Alexandre Belloni <alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
> arch/arm/boot/dts/berlin2.dtsi | 10 ++++++++++
> arch/arm/boot/dts/berlin2q.dtsi | 10 ++++++++++
> 2 files changed, 20 insertions(+)
>
> diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
> index 56a1af2f1052..4d85312dc17a 100644
> --- a/arch/arm/boot/dts/berlin2.dtsi
> +++ b/arch/arm/boot/dts/berlin2.dtsi
> @@ -72,6 +72,11 @@
> cache-level = <2>;
> };
>
> + scu: snoop-control-unit@ad0000 {
> + compatible = "arm,cortex-a9-scu";
> + reg = <0xad0000 0x58>;
> + };
> +
> gic: interrupt-controller@ad1000 {
> compatible = "arm,cortex-a9-gic";
> reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
> @@ -176,6 +181,11 @@
> };
> };
>
> + generic-regs@ea0184 {
> + compatible = "marvell,berlin-generic-regs", "syscon";
> + reg = <0xea0184 0x10>;
> + };
> +
> apb@fc0000 {
> compatible = "simple-bus";
> #address-cells = <1>;
> diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
> index 07452a7483fa..86d8a2c49f38 100644
> --- a/arch/arm/boot/dts/berlin2q.dtsi
> +++ b/arch/arm/boot/dts/berlin2q.dtsi
> @@ -87,6 +87,11 @@
> cache-level = <2>;
> };
>
> + scu: snoop-control-unit@ad0000 {
> + compatible = "arm,cortex-a9-scu";
> + reg = <0xad0000 0x58>;
> + };
> +
> local-timer@ad0600 {
> compatible = "arm,cortex-a9-twd-timer";
> reg = <0xad0600 0x20>;
> @@ -183,6 +188,11 @@
> };
> };
>
> + generic-regs@ea0110 {
> + compatible = "marvell,berlin-generic-regs", "syscon";
> + reg = <0xea0110 0x10>;
> + };
> +
> apb@fc0000 {
> compatible = "simple-bus";
> #address-cells = <1>;
>
--
Antoine Ténart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
--
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WARNING: multiple messages have this Message-ID (diff)
From: "Antoine Ténart" <antoine.tenart@free-electrons.com>
To: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
Russell King <linux@arm.linux.org.uk>,
Alexandre Belloni <alexandre.belloni@free-electrons.com>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] ARM: berlin: add scu and chipctrl device nodes for BG2/BG2Q
Date: Fri, 21 Mar 2014 10:20:24 +0100 [thread overview]
Message-ID: <532C0458.1090906@free-electrons.com> (raw)
In-Reply-To: <1395347986-30203-2-git-send-email-sebastian.hesselbarth@gmail.com>
On 20/03/2014 21:39, Sebastian Hesselbarth wrote:
> This adds scu and general purpose registers device nodes required for
> SMP on Berlin BG2 and BG2Q SoCs. The secondary CPUs will pick their jump
> address from general purpose (SW generic) register 1.
>
> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Antoine Ténart <antoine.tenart@free-electrons.com>
Also tested on the BG2Q,
Tested-by: Antoine Ténart <antoine.tenart@free-electrons.com>
> ---
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Pawel Moll <pawel.moll@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
> Cc: Kumar Gala <galak@codeaurora.org>
> Cc: Russell King <linux@arm.linux.org.uk>
> Cc: Antoine Tenart <antoine.tenart@free-electrons.com>
> Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> Cc: devicetree@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> ---
> arch/arm/boot/dts/berlin2.dtsi | 10 ++++++++++
> arch/arm/boot/dts/berlin2q.dtsi | 10 ++++++++++
> 2 files changed, 20 insertions(+)
>
> diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
> index 56a1af2f1052..4d85312dc17a 100644
> --- a/arch/arm/boot/dts/berlin2.dtsi
> +++ b/arch/arm/boot/dts/berlin2.dtsi
> @@ -72,6 +72,11 @@
> cache-level = <2>;
> };
>
> + scu: snoop-control-unit@ad0000 {
> + compatible = "arm,cortex-a9-scu";
> + reg = <0xad0000 0x58>;
> + };
> +
> gic: interrupt-controller@ad1000 {
> compatible = "arm,cortex-a9-gic";
> reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
> @@ -176,6 +181,11 @@
> };
> };
>
> + generic-regs@ea0184 {
> + compatible = "marvell,berlin-generic-regs", "syscon";
> + reg = <0xea0184 0x10>;
> + };
> +
> apb@fc0000 {
> compatible = "simple-bus";
> #address-cells = <1>;
> diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
> index 07452a7483fa..86d8a2c49f38 100644
> --- a/arch/arm/boot/dts/berlin2q.dtsi
> +++ b/arch/arm/boot/dts/berlin2q.dtsi
> @@ -87,6 +87,11 @@
> cache-level = <2>;
> };
>
> + scu: snoop-control-unit@ad0000 {
> + compatible = "arm,cortex-a9-scu";
> + reg = <0xad0000 0x58>;
> + };
> +
> local-timer@ad0600 {
> compatible = "arm,cortex-a9-twd-timer";
> reg = <0xad0600 0x20>;
> @@ -183,6 +188,11 @@
> };
> };
>
> + generic-regs@ea0110 {
> + compatible = "marvell,berlin-generic-regs", "syscon";
> + reg = <0xea0110 0x10>;
> + };
> +
> apb@fc0000 {
> compatible = "simple-bus";
> #address-cells = <1>;
>
--
Antoine Ténart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
next prev parent reply other threads:[~2014-03-21 9:20 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-20 20:39 [PATCH 0/2] ARM: berlin: SMP support Sebastian Hesselbarth
2014-03-20 20:39 ` Sebastian Hesselbarth
2014-03-20 20:39 ` Sebastian Hesselbarth
2014-03-20 20:39 ` [PATCH 1/2] ARM: berlin: add scu and chipctrl device nodes for BG2/BG2Q Sebastian Hesselbarth
2014-03-20 20:39 ` Sebastian Hesselbarth
2014-03-20 20:39 ` Sebastian Hesselbarth
2014-03-20 23:33 ` Alexandre Belloni
2014-03-20 23:33 ` Alexandre Belloni
2014-03-20 23:33 ` Alexandre Belloni
2014-03-21 9:20 ` Antoine Ténart [this message]
2014-03-21 9:20 ` Antoine Ténart
2014-03-21 9:20 ` Antoine Ténart
2014-04-16 19:03 ` Sebastian Hesselbarth
2014-04-16 19:03 ` Sebastian Hesselbarth
2014-04-16 19:03 ` Sebastian Hesselbarth
2014-03-20 20:39 ` [PATCH 2/2] ARM: berlin: add SMP support Sebastian Hesselbarth
2014-03-20 20:39 ` Sebastian Hesselbarth
2014-03-20 23:36 ` Alexandre Belloni
2014-03-20 23:36 ` Alexandre Belloni
2014-03-21 9:20 ` Antoine Ténart
2014-03-21 9:20 ` Antoine Ténart
2014-04-16 19:05 ` Sebastian Hesselbarth
2014-04-16 19:05 ` Sebastian Hesselbarth
2014-03-21 3:14 ` [PATCH 0/2] ARM: berlin: " Jisheng Zhang
2014-03-21 3:14 ` Jisheng Zhang
2014-03-21 9:44 ` Ben Dooks
2014-03-21 9:44 ` Ben Dooks
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