Re: [Qemu-devel] [PATCH 10/26] tcg-aarch64: Use CBZ and CBNZ

[Claudio Fontana <claudio.fontana@huawei.com>]

On 15.03.2014 03:48, Richard Henderson wrote:
> A compare and branch against zero happens at the start of
> every single TB.
> 
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/aarch64/tcg-target.c | 26 ++++++++++++++++++++++++--
>  1 file changed, 24 insertions(+), 2 deletions(-)
> 
> diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
> index 44d53aa..0d6d495 100644
> --- a/tcg/aarch64/tcg-target.c
> +++ b/tcg/aarch64/tcg-target.c
> @@ -270,6 +270,10 @@ enum aarch64_ldst_op_type { /* type of operation */
>     use the section number of the architecture reference manual in which the
>     instruction group is described.  */
>  typedef enum {
> +    /* Compare and branch (immediate).  */
> +    I3201_CBZ       = 0x34000000,
> +    I3201_CBNZ      = 0x35000000,
> +
>      /* Conditional branch (immediate).  */
>      I3202_B_C       = 0x54000000,
>  
> @@ -433,6 +437,12 @@ static inline uint32_t tcg_in32(TCGContext *s)
>  #define tcg_out_insn(S, FMT, OP, ...) \
>      glue(tcg_out_insn_,FMT)(S, glue(glue(glue(I,FMT),_),OP), ## __VA_ARGS__)
>  
> +static void tcg_out_insn_3201(TCGContext *s, AArch64Insn insn, TCGType ext,
> +                              TCGReg rt, int imm19)
> +{
> +    tcg_out32(s, insn | ext << 31 | (imm19 & 0x7ffff) << 5 | rt);
> +}
> +
>  static void tcg_out_insn_3202(TCGContext *s, AArch64Insn insn,
>                                TCGCond c, int imm19)
>  {
> @@ -910,8 +920,14 @@ static void tcg_out_brcond(TCGContext *s, TCGMemOp ext, TCGCond c, TCGArg a,
>  {
>      TCGLabel *l = &s->labels[label];
>      intptr_t offset;
> +    bool need_cmp;
>  
> -    tcg_out_cmp(s, ext, a, b, b_const);
> +    if (b_const && b == 0 && (c == TCG_COND_EQ || c == TCG_COND_NE)) {
> +        need_cmp = false;
> +    } else {
> +        need_cmp = true;
> +        tcg_out_cmp(s, ext, a, b, b_const);
> +    }
>  
>      if (!l->has_value) {
>          tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, label, 0);
> @@ -922,7 +938,13 @@ static void tcg_out_brcond(TCGContext *s, TCGMemOp ext, TCGCond c, TCGArg a,
>          assert(offset >= -0x40000 && offset < 0x40000);
>      }
>  
> -    tcg_out_insn(s, 3202, B_C, c, offset);
> +    if (need_cmp) {
> +        tcg_out_insn(s, 3202, B_C, c, offset);
> +    } else if (c == TCG_COND_EQ) {
> +        tcg_out_insn(s, 3201, CBZ, ext, a, offset);
> +    } else {
> +        tcg_out_insn(s, 3201, CBNZ, ext, a, offset);
> +    }
>  }
>  
>  static inline void tcg_out_rev(TCGContext *s, TCGType ext,
> 

Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>