From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41819) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WSUXy-00026x-UX for qemu-devel@nongnu.org; Tue, 25 Mar 2014 12:54:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WSUUc-0007Uq-9h for qemu-devel@nongnu.org; Tue, 25 Mar 2014 12:49:54 -0400 Received: from cantor2.suse.de ([195.135.220.15]:47999 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WSUUc-0007Uf-3c for qemu-devel@nongnu.org; Tue, 25 Mar 2014 12:46:26 -0400 Message-ID: <5331B2E0.3090902@suse.de> Date: Tue, 25 Mar 2014 17:46:24 +0100 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1395764877-10487-1-git-send-email-ard.biesheuvel@linaro.org> In-Reply-To: <1395764877-10487-1-git-send-email-ard.biesheuvel@linaro.org> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] target-arm: add support for v8 SHA1 and SHA256 instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Ard Biesheuvel , qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: christoffer.dall@linaro.org Am 25.03.2014 17:27, schrieb Ard Biesheuvel: > This adds support for the SHA1 and SHA256 instructions that are availab= le > on some v8 implementations of Aarch32. >=20 > Signed-off-by: Ard Biesheuvel > --- > target-arm/cpu.c | 2 + > target-arm/cpu.h | 2 + > target-arm/crypto_helper.c | 257 +++++++++++++++++++++++++++++++++++++= ++++++-- > target-arm/helper.h | 9 ++ > target-arm/translate.c | 81 ++++++++++++++ > 5 files changed, 344 insertions(+), 7 deletions(-) >=20 > diff --git a/target-arm/cpu.c b/target-arm/cpu.c > index c32d8c4855b4..58c4584ac3bc 100644 > --- a/target-arm/cpu.c > +++ b/target-arm/cpu.c > @@ -291,6 +291,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) > set_feature(env, ARM_FEATURE_ARM_DIV); > set_feature(env, ARM_FEATURE_LPAE); > set_feature(env, ARM_FEATURE_V8_AES); > + set_feature(env, ARM_FEATURE_V8_SHA1); > + set_feature(env, ARM_FEATURE_V8_SHA256); > } > if (arm_feature(env, ARM_FEATURE_V7)) { > set_feature(env, ARM_FEATURE_VAPA); > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index bf37cd60d0a2..f5039d8b0177 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -630,6 +630,8 @@ enum arm_features { > ARM_FEATURE_V8_AES, /* implements AES part of v8 Crypto Extensions= */ > ARM_FEATURE_CBAR, /* has cp15 CBAR */ > ARM_FEATURE_CRC, /* ARMv8 CRC instructions */ > + ARM_FEATURE_V8_SHA1, /* implements SHA1 part of v8 Crypto Extensio= ns */ > + ARM_FEATURE_V8_SHA256, /* implements SHA256 part of v8 Crypto Exte= nsions */ > }; Do these really need to be separate features? We only have 32 feature bits. Maybe even an ARM_FEATURE_CRYPTO for AES, SHA1, SHA256 would do? Regards, Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg