From: gregory.clement@free-electrons.com (Gregory CLEMENT)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 00/44] outer cache changes
Date: Wed, 26 Mar 2014 21:05:43 +0100 [thread overview]
Message-ID: <53333317.7020900@free-electrons.com> (raw)
In-Reply-To: <20140317001302.GY21483@n2100.arm.linux.org.uk>
Hi Russell,
On 17/03/2014 01:13, Russell King - ARM Linux wrote:
> This patch series is where I'm currently at with the total mess which
> is L2 cache support. That's putting it mildly. This isn't intended
> for anyone to pick up - this is still mostly in development.
>
> I need help with the Aurora/Tauros3/Broadcom stuff, as that remains
> addicted to the old buggy code that we used to have (eg, if you build
> a v6+v7 kernel, all PL310 errata get disabled. If CONFIG_CACHE_PL310
> is enabled and you actually have a L2C-220, the necessary waits will
> be omitted. If you enable erratum 588369 and set the .set_debug
> method to NULL or have a PL310 later than R3P0, you're opening a
> race condition. etc.)
>
> One of the potentially explosive issues is the utter crap and fscked
> state of DT implementation here, much of which /can't/ now be fixed
> without breaking existing DT based booting with existing files,
> because we have a mixture of DT properties combined with platform
> specific code setting various L2C configuration parameters (sometimes
> writing directly to the registers.)
>
> For example, I've made a start at trying to prevent any further additions
> of platform code writing to the L2C-310's power control register by
> adding a couple of properties - but we can't delete the direct register
> write in iMX6 code without breaking existing DT descriptions.
>
> The same goes for the mess which is the auxillary control register,
> or now the prefetch control register. Or the erratum 752271 which
> iMX6 implements in their own SoC specific code.
>
> Here's the *big* explosive question: how have we ended up in this mess?
> A bigger question: why was none of this caught at review time? An even
> bigger question (which I believe is at the root of much of the pain that
> people feel with DT): why aren't device properties being thought out
> better - by that I mean, why isn't the question "are the properties you
> are proposing for device X sufficient to describe all it's configurable
> parameters, and if not, what are you omitting?" being asked when new
> device bindings are being proposed.
>
> You can see the extent of the L2C crap from the diffstat below - every
> arch/arm/mach-* file touched here is a symptom of failing to adequately
> describe the properties that platforms need to specify. It's a failing
> of DT process. It's a failing of review of SoC code.
>
I had a quick look on this series and it is a really good improvement of
the code. I didn't notice anything suspicious regarding the Aurora L2
cache controller.
Then I have applied this series on 3.14-rc8 using our mvebu_defconfig. And
made some performance tests using cachebench. So I tested it on:
- an Armada XP based board which use the Aurora cache controller with the
aurora-system-cache flavor.
- an Armada 370 based board which use the Aurora cache controller with the
aurora-outer-cache.
I didn't notice any regression in both case.
So at least you can add my
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Thanks for your work,
Gregory
> Anyway, here's the diffstat so far. Not Cc'ing anyone this time around
> (the Cc list is huge), so it's all on LAKML.
>
> Documentation/devicetree/bindings/arm/l2cc.txt | 2 +
> arch/arm/Kconfig | 51 -
> arch/arm/boot/dts/imx6qdl.dtsi | 2 +
> arch/arm/boot/dts/imx6sl.dtsi | 2 +
> arch/arm/include/asm/hardware/cache-l2x0.h | 63 +-
> arch/arm/include/asm/outercache.h | 67 +-
> arch/arm/mach-cns3xxx/core.c | 8 +-
> arch/arm/mach-highbank/highbank.c | 12 +-
> arch/arm/mach-imx/system.c | 8 +-
> arch/arm/mach-omap2/omap-mpuss-lowpower.c | 2 +-
> arch/arm/mach-omap2/omap4-common.c | 58 +-
> arch/arm/mach-prima2/l2x0.c | 5 +-
> arch/arm/mach-prima2/pm.c | 1 -
> arch/arm/mach-realview/realview_pbx.c | 4 +-
> arch/arm/mach-spear/platsmp.c | 19 +-
> arch/arm/mach-spear/spear13xx.c | 6 +-
> arch/arm/mach-sti/board-dt.c | 8 +-
> arch/arm/mach-tegra/sleep.h | 8 +-
> arch/arm/mach-ux500/cache-l2x0.c | 23 +-
> arch/arm/mach-vexpress/ct-ca9x4.c | 4 +-
> arch/arm/mm/Kconfig | 51 +
> arch/arm/mm/Makefile | 1 +
> arch/arm/mm/cache-feroceon-l2.c | 1 -
> arch/arm/mm/cache-l2x0.c | 1354 +++++++++++++++++-------
> arch/arm/mm/l2c-common.c | 20 +
> arch/arm/plat-samsung/s5p-sleep.S | 8 +-
> 26 files changed, 1221 insertions(+), 567 deletions(-)
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
next prev parent reply other threads:[~2014-03-26 20:05 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-17 0:13 [PATCH 00/44] outer cache changes Russell King - ARM Linux
2014-03-17 0:13 ` [PATCH 01/44] ARM: l2c: remove outer_inv_all() method Russell King
2014-03-17 0:13 ` [PATCH 02/44] ARM: l2c: remove unnecessary call to outer_flush_all() Russell King
2014-03-17 0:13 ` [PATCH 03/44] ARM: l2c: avoid calling outer_flush_all() unnecessarily (Spear) Russell King
2014-03-17 0:13 ` [PATCH 04/44] ARM: l2c: add helper for L2 cache controller DT IDs Russell King
2014-03-26 20:30 ` Rob Herring
2014-03-17 0:13 ` [PATCH 05/44] ARM: l2c: tidy up l2x0_of_data declarations Russell King
2014-03-17 0:14 ` [PATCH 06/44] ARM: l2c: rename OF specific things, making l2x0_of_data available to all Russell King
2014-03-17 0:14 ` [PATCH 07/44] ARM: l2c: provide generic function for calling set_debug method Russell King
2014-03-17 0:14 ` [PATCH 08/44] ARM: l2c: split out cache unlock code Russell King
2014-03-17 0:14 ` [PATCH 09/44] ARM: l2c: provide generic helper for way-based operations Russell King
2014-03-17 0:14 ` [PATCH 10/44] ARM: l2c: rename cache_wait_way() Russell King
2014-03-17 0:14 ` [PATCH 11/44] ARM: l2c: use add L2C revision constants Russell King
2014-03-17 0:14 ` [PATCH 12/44] ARM: l2c: clean up OF initialisation a bit Russell King
2014-03-17 0:14 ` [PATCH 13/44] ARM: l2c: pass iomem address into data->save function Russell King
2014-03-17 0:14 ` [PATCH 14/44] ARM: l2c: move l2c save function to __l2c_init() Russell King
2014-03-17 0:14 ` [PATCH 15/44] ARM: l2c: provide enable method Russell King
2014-03-17 0:14 ` [PATCH 16/44] ARM: l2c: move aurora broadcast setup to enable function Russell King
2014-03-17 0:14 ` [PATCH 17/44] ARM: l2c: group implementation specific code together Russell King
2014-03-17 0:15 ` [PATCH 18/44] ARM: l2c: implement fixups for L2 cache controller quirks/errata Russell King
2014-03-17 0:15 ` [PATCH 19/44] ARM: l2c: clean up L2 cache initialisation messages Russell King
2014-03-17 0:15 ` [PATCH 20/44] ARM: l2c: split L2C-310 enable function from l2x0 code Russell King
2014-03-17 0:15 ` [PATCH 21/44] ARM: l2c: move and add ARM L2C-2x0/L2C-310 save/resume code to non-OF Russell King
2014-03-17 0:15 ` [PATCH 22/44] ARM: l2c: clean up save/resume functions Russell King
2014-03-17 0:15 ` [PATCH 23/44] ARM: l2c: simplify l2x0 unlocking code Russell King
2014-03-17 0:15 ` [PATCH 24/44] ARM: l2c: move pl310_set_debug() into l2c-310 code Russell King
2014-03-17 0:15 ` [PATCH 25/44] ARM: l2c: add L2C-210 specific handlers Russell King
2014-03-17 0:15 ` [PATCH 26/44] ARM: l2c: implement L2C-310 erratum 727915 as a method override Russell King
2014-03-17 0:15 ` [PATCH 27/44] ARM: l2c: Implement L2C-310 erratum 588369 " Russell King
2014-03-17 0:15 ` [PATCH 28/44] ARM: l2c: use L2C-210 handlers for L2C-310 errata-less implementations Russell King
2014-03-17 0:15 ` [PATCH 29/44] ARM: l2c: add L2C-220 specific handlers Russell King
2014-03-17 0:16 ` [PATCH 30/44] ARM: l2c: remove obsolete l2x0 ops for non-OF init Russell King
2014-03-17 0:16 ` [PATCH 31/44] ARM: l2c: move type string into l2c_init_data structure Russell King
2014-03-17 0:16 ` [PATCH 32/44] ARM: l2c: add decode for L2C-220 cache ways Russell King
2014-03-17 0:16 ` [PATCH 33/44] ARM: l2c: move way size calculation data into l2c_init_data Russell King
2014-03-17 0:16 ` [PATCH 34/44] ARM: outer cache: add documentation of outer cache functions Russell King
2014-03-17 0:16 ` [PATCH 35/44] ARM: outer cache: add WARN_ON() to outer_disable() Russell King
2014-03-17 0:16 ` [PATCH 36/44] ARM: l2c: move errata configuration options to arch/arm/mm/Kconfig Russell King
2014-03-17 0:16 ` [PATCH 37/44] ARM: l2c: provide generic hook to intercept writes to secure registers Russell King
2014-03-17 0:16 ` [PATCH 38/44] ARM: l2c: OMAP: implement new write_sec method Russell King
2014-03-17 0:16 ` [PATCH 39/44] ARM: l2c: highbank: " Russell King
2014-03-26 20:35 ` Rob Herring
2014-03-17 0:16 ` [PATCH 40/44] ARM: l2c: ux500: implement dummy " Russell King
2014-03-17 0:17 ` [PATCH 41/44] ARM: l2c: remove old .set_debug method Russell King
2014-03-17 0:17 ` [PATCH 42/44] ARM: l2c: implement L2C-310 erratum 752271 in core L2C code Russell King
2014-03-17 0:17 ` [PATCH 43/44] ARM: l2c: rename all L2C-310 constants with an L310_ prefix Russell King
2014-03-17 0:17 ` [PATCH 44/44] ARM: l2c: add L2C-310 power control DT properties Russell King
2014-03-26 21:08 ` Rob Herring
2014-03-28 13:29 ` Russell King - ARM Linux
2014-03-26 20:05 ` Gregory CLEMENT [this message]
2014-03-28 18:50 ` [PATCH 00/44] outer cache changes Nishanth Menon
2014-03-28 18:50 ` Nishanth Menon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=53333317.7020900@free-electrons.com \
--to=gregory.clement@free-electrons.com \
--cc=linux-arm-kernel@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.