From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jamal Hadi Salim <jhs@mojatatu.com>
Subject: Re: [patch net-next RFC 0/4] introduce infrastructure for support
 of switch chip datapath
Date: Wed, 26 Mar 2014 18:53:51 -0400
Message-ID: <53335A7F.8010801@mojatatu.com>
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Cc: Jiri Pirko <jiri@resnulli.us>,
	Roopa Prabhu <roopa@cumulusnetworks.com>,
	Neil Horman <nhorman@tuxdriver.com>,
	Thomas Graf <tgraf@suug.ch>, netdev <netdev@vger.kernel.org>,
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	jeffrey.t.kirsher@intel.com, vyasevic <vyasevic@redhat.com>,
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	Scott Feldman <sfeldma@cumulusnetworks.com>,
	Lennert Buytenhek <buytenh@wantstofly.org>,
	Shrijeet Mukherjee <shm@cumulusnetworks.com>,
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To: Florian Fainelli <f.fainelli@gmail.com>
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On 03/26/14 18:22, Florian Fainelli wrote:
> 2014-03-26 14:51 GMT-07:00 Jamal Hadi Salim <jhs@mojatatu.com>:

>
> eth0 corresponds to a CPU Ethernet MAC facing e.g: sw1p3 switch port.
> It is "regular" Ethernet driver connected to the switch without
> switch-specific logic. The goal is twofold:
>
> - allow any regular Ethernet driver to be connected to an external
> switch via e.g: MDIO/MDC or other without specific switch knowledge
> - represents accurately how the hardware is designed/connected
>

Gah. Sorry - I missed the MII interface.
In such a case as shown here then, how do you control sw1p0-3?

> but maybe, we can simplify and have e.g: sw1p3 and eth0 be the same interface...

It sounds to me the CPU side is only a driver for sw1p3.

>>
>> Note: even the high end chips tend to have the concept of a "cpu port"
>> but my experience is to hide that as part of the switch driver.

Note: the high end devices "cpu ports" are accessible typically
via PCIE interfaces for control and some DMA for data activity.

cheers,
jamal