From: Alexey Kardashevskiy <aik@ozlabs.ru>
To: Anton Blanchard <anton@samba.org>,
qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Cc: clg@fr.ibm.com, gkurz@linux.vnet.ibm.com
Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 6/6] target-ppc: Add PMC7/8 to 970
Date: Fri, 28 Mar 2014 00:03:34 +1100 [thread overview]
Message-ID: <533421A6.6030007@ozlabs.ru> (raw)
In-Reply-To: <1395715231-4217-6-git-send-email-anton@samba.org>
On 03/25/2014 01:40 PM, Anton Blanchard wrote:
> 970 CPUs have PMC7/8. Create gen_spr_970 to avoid replicating
> it 3 times, and simplify the existing code.
>
> Signed-off-by: Anton Blanchard <anton@samba.org>
> ---
> target-ppc/translate_init.c | 89 ++++++++++++++++++++-------------------------
> 1 file changed, 39 insertions(+), 50 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 273e37d..50b2603 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -6747,12 +6747,13 @@ static void gen_spr_book3s (CPUPPCState *env)
> 0x00000000);
> }
>
> -static void init_proc_970 (CPUPPCState *env)
> +static void gen_spr_970 (CPUPPCState *env)
> {
> - gen_spr_ne_601(env);
> - gen_spr_book3s(env);
> - /* Time base */
> - gen_tbl(env);
> + spr_register(env, SPR_HIOR, "SPR_HIOR",
+ spr_register(env, SPR_HIOR, "HIOR",
Can we please not add SPR_ in string name? Thanks.
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_hior, &spr_write_hior,
> + 0x00000000);
> +
> /* Hardware implementation registers */
> /* XXX : not implemented */
> spr_register(env, SPR_HID0, "HID0",
> @@ -6769,13 +6770,40 @@ static void init_proc_970 (CPUPPCState *env)
> SPR_NOACCESS, SPR_NOACCESS,
> &spr_read_generic, &spr_write_generic,
> POWERPC970_HID5_INIT);
> +
> + /* Performance monitors */
> + /* XXX : not implemented */
> + spr_register_kvm(env, SPR_BOOK3S_PMC7, "PMC7",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_PMC7, 0x00000000);
> + /* XXX : not implemented */
> + spr_register_kvm(env, SPR_BOOK3S_PMC8, "PMC8",
> + SPR_NOACCESS, SPR_NOACCESS,
> + &spr_read_generic, &spr_write_generic,
> + KVM_REG_PPC_PMC8, 0x00000000);
> + /* XXX : not implemented */
> + spr_register(env, SPR_BOOK3S_UPMC7, "UPMC7",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> + /* XXX : not implemented */
> + spr_register(env, SPR_BOOK3S_UPMC8, "UPMC8",
> + &spr_read_ureg, SPR_NOACCESS,
> + &spr_read_ureg, SPR_NOACCESS,
> + 0x00000000);
> +}
> +
> +static void init_proc_970 (CPUPPCState *env)
> +{
> + gen_spr_ne_601(env);
> + gen_spr_book3s(env);
> + gen_spr_970(env);
> + /* Time base */
> + gen_tbl(env);
> /* Memory management */
> /* XXX: not correct */
> gen_low_BATs(env);
> - spr_register(env, SPR_HIOR, "SPR_HIOR",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_hior, &spr_write_hior,
> - 0x00000000);
> #if !defined(CONFIG_USER_ONLY)
> env->slb_nr = 32;
> #endif
> @@ -6831,31 +6859,12 @@ static void init_proc_970FX (CPUPPCState *env)
> {
> gen_spr_ne_601(env);
> gen_spr_book3s(env);
> + gen_spr_970(env);
> /* Time base */
> gen_tbl(env);
> - /* Hardware implementation registers */
> - /* XXX : not implemented */
> - spr_register(env, SPR_HID0, "HID0",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_clear,
> - 0x60000000);
> - /* XXX : not implemented */
> - spr_register(env, SPR_HID1, "HID1",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> - /* XXX : not implemented */
> - spr_register(env, SPR_970_HID5, "HID5",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - POWERPC970_HID5_INIT);
> /* Memory management */
> /* XXX: not correct */
> gen_low_BATs(env);
> - spr_register(env, SPR_HIOR, "SPR_HIOR",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_hior, &spr_write_hior,
> - 0x00000000);
> spr_register(env, SPR_CTRL, "SPR_CTRL",
> SPR_NOACCESS, SPR_NOACCESS,
> SPR_NOACCESS, &spr_write_generic,
> @@ -6923,32 +6932,12 @@ static void init_proc_970MP (CPUPPCState *env)
> {
> gen_spr_ne_601(env);
> gen_spr_book3s(env);
> + gen_spr_970(env);
> /* Time base */
> gen_tbl(env);
> - /* Hardware implementation registers */
> - /* XXX : not implemented */
> - spr_register(env, SPR_HID0, "HID0",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_clear,
> - 0x60000000);
> - /* XXX : not implemented */
> - spr_register(env, SPR_HID1, "HID1",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - 0x00000000);
> - /* XXX : not implemented */
> - spr_register(env, SPR_970_HID5, "HID5",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_generic, &spr_write_generic,
> - POWERPC970_HID5_INIT);
> - /* XXX : not implemented */
> /* Memory management */
> /* XXX: not correct */
> gen_low_BATs(env);
> - spr_register(env, SPR_HIOR, "SPR_HIOR",
> - SPR_NOACCESS, SPR_NOACCESS,
> - &spr_read_hior, &spr_write_hior,
> - 0x00000000);
> /* Logical partitionning */
> spr_register_kvm(env, SPR_LPCR, "LPCR",
> SPR_NOACCESS, SPR_NOACCESS,
>
--
Alexey
next prev parent reply other threads:[~2014-03-27 13:03 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-25 2:40 [Qemu-devel] [PATCH 1/6] target-ppc: POWER8 supports the MSR_LE bit Anton Blanchard
2014-03-25 2:40 ` [Qemu-devel] [PATCH 2/6] target-ppc: POWER8 supports isel Anton Blanchard
2014-03-25 2:40 ` [Qemu-devel] [PATCH 3/6] target-ppc: POWER7+ supports the MSR_VSX bit Anton Blanchard
2014-03-25 2:40 ` [Qemu-devel] [PATCH 4/6] target-ppc: MSR_POW not supported on POWER7/7+/8 Anton Blanchard
2014-03-25 2:40 ` [Qemu-devel] [PATCH 5/6] target-ppc: Fix Book3S PMU SPRs Anton Blanchard
2014-04-10 13:22 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2014-03-25 2:40 ` [Qemu-devel] [PATCH 6/6] target-ppc: Add PMC7/8 to 970 Anton Blanchard
2014-03-27 13:03 ` Alexey Kardashevskiy [this message]
2014-03-27 15:40 ` [Qemu-devel] [Qemu-ppc] " Andreas Färber
2014-04-10 13:24 ` Alexander Graf
2014-03-25 7:29 ` [Qemu-devel] [PATCH 1/6] target-ppc: POWER8 supports the MSR_LE bit Alex Bennée
2014-03-27 14:58 ` Andreas Färber
2014-03-27 17:10 ` Tom Musta
2014-03-27 15:36 ` Andreas Färber
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