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From: Olivier MATZ <olivier.matz-pdR9zngts4EAvxtiuMwx3w@public.gmane.org>
To: Stephen Hemminger
	<stephen-OTpzqLSitTUnbdJkjeBofR2eb7JE58TQ@public.gmane.org>
Cc: "dev-VfR2kkLFssw@public.gmane.org" <dev-VfR2kkLFssw@public.gmane.org>
Subject: Re: memory barriers in rte_ring
Date: Thu, 27 Mar 2014 20:47:37 +0100	[thread overview]
Message-ID: <53348059.6000505@6wind.com> (raw)
In-Reply-To: <20140327120620.07f1496b@samsung-9>

Hi Stephen,

On 03/27/2014 08:06 PM, Stephen Hemminger wrote:
> Long answer: for the multple CPU access ring, it is equivalent to smp_wmb and smp_rmb
>   in Linux kernel. For x86 where DPDK is used, this can normally be replaced by simpler
>   compiler barrier. In kernel there is a special flage X86_OOSTORE which is only enabled
>   for a few special cases, for most cases it is not. When cpu doesnt do out of order
>   stores, there are no cases where other cpu will see wrong state.

Thank you for this clarification.

So, if I understand properly, all usages of rte_*mb() sequencing memory
operations between CPUs could be replaced by a compiler barrier. On the
other hand, if the memory is also accessed by a device, a memory
barrier has to be used.

Olivier

  reply	other threads:[~2014-03-27 19:47 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-03-27 16:48 memory barriers in rte_ring Olivier MATZ
     [not found] ` <53345655.9030907-pdR9zngts4EAvxtiuMwx3w@public.gmane.org>
2014-03-27 19:06   ` Stephen Hemminger
2014-03-27 19:47     ` Olivier MATZ [this message]
     [not found]       ` <53348059.6000505-pdR9zngts4EAvxtiuMwx3w@public.gmane.org>
2014-03-27 20:20         ` Stephen Hemminger
2014-03-27 23:53           ` Venkatesan, Venky

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