Re: [Qemu-devel] [Qemu-ppc] target-ppc: Problem with mtmsr emulation

[Tom Musta <tommusta@gmail.com>]

On 3/28/2014 7:02 AM, Thomas Huth wrote:
> On Fri, 28 Mar 2014 18:25:02 +0800
> Alexander Graf <agraf@suse.de> wrote:
> 
>>
>>
>>> Am 28.03.2014 um 16:16 schrieb Thomas Huth <thuth@linux.vnet.ibm.com>:
>>>

<snip>

>>> An easy way to fix this for Book III-S is to change the mask to
>>> 0x001EF801 (just like the mask for mtmsrd), but I am afraid that this
>>> would break the Book III-E variant of mtmsr, since the embedded version
>>> does not have this bit defined. Any suggestions how to fix this problem
>>> in a proper way?
>>
>> Please check in the older isa versions whether that bit is declared reserved.
>>
>> If it is, we need to make sure we only match it on newer ISA conformance.
> 
> The oldest ISA version that I've found (version 2.01, from 2003) already
> contains the L bit, so I assume it's always been there. So it's likely
> just a Book III-S vs. Book III-E issue.
> 

The L bit was not part of the original PowerPC ISA.  I checked both my 604 manual
((C) 1993) and the May, Silha, Simpson, Warren book ((C) 1994) ... neither contains
the L bit.  So the *actual* delineation is not as simple as Book III-S vs. Book
III-E.  I suspect the change was introduced in the mid-2000's.

To make matters worse, the change was incompatible with the previous versions of
the architecture -- The L=1 case is the old behavior (copy source register bits
verbatim, execution synchronizing) whereas L=0 is the new behavior (force external
interrupts and virtual address translation in user-state, context synchronizing).
And, the L=1 case on Book-IIIS is more like the L=0 case in Book-IIIE.

Also, I do not (yet) see the actual implementation of the Book-IIIS L=0 behavior
in the QEMU code.  This bug is probably masked by the fact that folks who use
mtmsr probably know what they are doing -- i.e. who would try to enable user-mode
and not enabled address translation?

Egads, what a mess.

I agree with Alex that a flags based approach could be used to support the L bit for
Book III-S models and to ignore the L bit for Book III-E models.  The question is
which flag(s) can we use?  Let me see if I can find out.