From mboxrd@z Thu Jan 1 00:00:00 1970 From: Aravind Gopalakrishnan Subject: Re: [PATCH RFC 0/4] x86/AMD: support newer hardware features Date: Tue, 1 Apr 2014 18:10:33 -0500 Message-ID: <533B4769.6030102@amd.com> References: <532880230200007800125450@nat28.tlf.novell.com> <53296E90020000780012593B@nat28.tlf.novell.com> <53296E90020000780012593B@nat28.tlf.novell.com> <5333561F.5050608@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Return-path: Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WV7pQ-0001Bn-Kz for xen-devel@lists.xenproject.org; Tue, 01 Apr 2014 23:10:48 +0000 In-Reply-To: <5333561F.5050608@amd.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Jan Beulich , "xen-devel@lists.xenproject.org" Cc: Ian.Jackson@eu.citrix.com, Keir Fraser , ian.campbell@citrix.com, "Suthikulpanit, Suravee" , "Hurwitz, Sherry" List-Id: xen-devel@lists.xenproject.org On 3/26/2014 5:35 PM, Aravind Gopalakrishnan wrote: >> >> 1: SVM: support data breakpoint extension registers >> 2: PV: support data breakpoint extension registers Tested-by: Aravind Gopalakrishnan >> 3: x86/AMD: support further feature masking MSRs >> 4: x86/AMD: clean up pre-canned family/revision handling for CPUID >> masking Reviewed-by: Aravind Gopalakrishnan >> >> Patches 3 and 4 are fully tested; for patches 1 and 2 I'm lacking >> suitable hardware, and hence depend on AMD's help (and patch >> 1 is also still lacking some tools side adjustments). Patch 3, otoh, >> has a couple of questions to be answered. Overall this makes the >> whole series RFC only for now. >> >> Signed-off-by: Jan Beulich >> > Thanks, -Aravind