From mboxrd@z Thu Jan 1 00:00:00 1970 From: Julien Grall Subject: Re: [PATCH 2/3] xen: arm: flush TLB on all CPUs when setting or clearing fixmaps Date: Wed, 02 Apr 2014 15:46:09 +0100 Message-ID: <533C22B1.1020202@linaro.org> References: <1396447908.8667.346.camel@kazak.uk.xensource.com> <1396447971-27846-2-git-send-email-ian.campbell@citrix.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1396447971-27846-2-git-send-email-ian.campbell@citrix.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org To: Ian Campbell Cc: stefano.stabellini@eu.citrix.com, tim@xen.org, xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org On 04/02/2014 03:12 PM, Ian Campbell wrote: > These mappings are global and therefore need flushing on all processors. Add > flush_all_xen_data_tlb_range_va which accomplishes this. I think remove_early_mappings should also use flush_xen_data_range_va. I'm wondering why BOOT_FDT_VIRT_START is removed so late (i.e in discard_initial_modules). It can be done once the DTB is copied in setup_mm. [..] > > +/* > + * Flush a range of VA's hypervisor mappings from the data TLB on all > + * processors in the inner-shareable domain. This is not sufficient > + * when changing code mappings or for self modifying code. > + */ > +static inline void flush_xen_data_tlb_range_va(unsigned long va, > + unsigned long size) > +{ > + unsigned long end = va + size; > + dsb(sy); /* Ensure preceding are visible */ > + while ( va < end ) { > + asm volatile(STORE_CP32(0, TLBIMVAHIS) > + : : "r" (va) : "memory"); > + va += PAGE_SIZE; > + } > + dsb(sy); /* Ensure completion of the TLB flush */ > + isb(); > +} > + This loop is exactly the same on arm64 (except the TLBIMVAHIS), is it possible to have a common code like clean_xen_dcache_va_range? Regards, -- Julien Grall