From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37665) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WX4Rx-0001WK-Ou for qemu-devel@nongnu.org; Mon, 07 Apr 2014 03:58:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WX4Ro-00019f-U9 for qemu-devel@nongnu.org; Mon, 07 Apr 2014 03:58:37 -0400 Received: from lhrrgout.huawei.com ([194.213.3.17]:14675) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WX4Ro-00015e-Km for qemu-devel@nongnu.org; Mon, 07 Apr 2014 03:58:28 -0400 Message-ID: <53425A88.2050806@huawei.com> Date: Mon, 7 Apr 2014 09:58:00 +0200 From: Claudio Fontana MIME-Version: 1.0 References: <1396555000-8205-1-git-send-email-rth@twiddle.net> <1396555000-8205-2-git-send-email-rth@twiddle.net> In-Reply-To: <1396555000-8205-2-git-send-email-rth@twiddle.net> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v3 01/26] tcg-aarch64: Properly detect SIGSEGV writes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson , qemu-devel@nongnu.org Cc: Peter Maydell , claudio.fontana@gmail.com On 03.04.2014 21:56, Richard Henderson wrote: > Since the kernel doesn't pass any info on the reason for the fault, > disassemble the instruction to detect a store. > > Signed-off-by: Richard Henderson > --- > user-exec.c | 29 +++++++++++++++++++++++------ > 1 file changed, 23 insertions(+), 6 deletions(-) > > diff --git a/user-exec.c b/user-exec.c > index bc58056..52f76c9 100644 > --- a/user-exec.c > +++ b/user-exec.c > @@ -465,16 +465,33 @@ int cpu_signal_handler(int host_signum, void *pinfo, > > #elif defined(__aarch64__) > > -int cpu_signal_handler(int host_signum, void *pinfo, > - void *puc) > +int cpu_signal_handler(int host_signum, void *pinfo, void *puc) > { > siginfo_t *info = pinfo; > struct ucontext *uc = puc; > - uint64_t pc; > - int is_write = 0; /* XXX how to determine? */ > + uintptr_t pc = uc->uc_mcontext.pc; > + uint32_t insn = *(uint32_t *)pc; > + bool is_write; > > - pc = uc->uc_mcontext.pc; > - return handle_cpu_signal(pc, (uint64_t)info->si_addr, > + /* XXX: need kernel patch to get write flag faster. */ > + /* XXX: several of these could be combined. */ > + is_write = ( (insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */ > + || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */ > + || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */ > + || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */ > + || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */ > + || (insn & 0x3bc00000) == 0x28400000 /* C3.3.7 */ I think the Load (L) bit should be 0 here so == 0x28000000 > + || (insn & 0x3be00c00) == 0x38000400 /* C3.3.8 */ With V=1, an opc of 0b10 is also a write, I think. It's the 128bit FP/SIMD STR. > + || (insn & 0x3be00c00) == 0x38000c00 /* C3.3.9 */ Same here. > + || (insn & 0x3be00c00) == 0x38200800 /* C3.3.10 */ Same. > + || (insn & 0x3be00c00) == 0x38000800 /* C3.3.11 */ > + || (insn & 0x3be00c00) == 0x38000000 /* C3.3.12 */ Same. > + || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */ Same. > + || (insn & 0x3bc00000) == 0x29000000 /* C3.3.14 */ > + || (insn & 0x3bc00000) == 0x28800000 /* C3.3.15 */ > + || (insn & 0x3bc00000) == 0x29800000); /* C3.3.16 */ > + > + return handle_cpu_signal(pc, (uintptr_t)info->si_addr, > is_write, &uc->uc_sigmask, puc); > } > > Thanks, Claudio