From: Tom Musta <tommusta@gmail.com>
To: Alexander Graf <agraf@suse.de>, qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v2] PPC: Clean up DECR implementation
Date: Tue, 08 Apr 2014 14:56:12 -0500 [thread overview]
Message-ID: <5344545C.7060608@gmail.com> (raw)
In-Reply-To: <1396817714-26768-1-git-send-email-agraf@suse.de>
On 4/6/2014 3:55 PM, Alexander Graf wrote:
<snip>
> @@ -806,6 +838,10 @@ clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq)
> tb_env = g_malloc0(sizeof(ppc_tb_t));
> env->tb_env = tb_env;
> tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
> + if (env->insns_flags & PPC_SEGMENT_64B) {
> + /* All Book3S 64bit CPUs implement level based DEC logic */
> + tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL;
> + }
> /* Create new timer */
> tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_decr_cb, cpu);
> if (0) {
Equating Book3S with PPC_SEGMENT_64B is clever ... is it too clever? Especially since
the SLB Bridge is in the phased-out category and consequently we should expect future
Book3S implementations to not support this instruction category.
next prev parent reply other threads:[~2014-04-08 19:56 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-06 20:55 [Qemu-devel] [PATCH v2] PPC: Clean up DECR implementation Alexander Graf
2014-04-08 19:56 ` Tom Musta [this message]
2014-04-08 19:58 ` Alexander Graf
2014-04-08 21:17 ` Tom Musta
2014-04-09 19:33 ` Tom Musta
2014-04-09 19:59 ` Alexander Graf
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