[U-Boot] [PATCH V2] mmc:eSDHC: Workaround for data timeout issue on Txxx SoC

[Zhang Haijun <b42677@freescale.com>]

Thanks a lot.

BTW, how about other patches?
I saw there are patches conflict with mine now.


Regards & Thanks

-- Haijun

On 04/02/2014 06:27 PM, Pantelis Antoniou wrote:
> Hi Haijun,
>
> The patch looks good but it doesn't apply after the mmc changes I've made
>
> I've reworked and applied it;
>
> On Mar 18, 2014, at 11:04 AM, Haijun Zhang wrote:
>
>> 1. The Data timeout counter value in eSDHC_SYSCTL register is
>> not working as it should be, so add quirks to enable this
>> workaround to fix it to the max value 0xE.
>>
>> 2. For eSDHC the Block Count size each transmission should not
>> exceed 0xFFFF blocks, Fix b_max to 0xFFFF to limit the transfer
>> size for read and write command.
>>
> ^ this is already handled by the default value of 0xffff
>
>> 3. Add CONFIG_SYS_FSL_ERRATUM_ESDHC111 to enable its workaround.
>>
>> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
>> ---
>> changes for V2
>> 	- Rewrite the comments.
>>
>
>> arch/powerpc/include/asm/config_mpc85xx.h | 5 +++++
>> drivers/mmc/fsl_esdhc.c                   | 5 ++++-
>> 2 files changed, 9 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
>> index 9a20b97..df44451 100644
>> --- a/arch/powerpc/include/asm/config_mpc85xx.h
>> +++ b/arch/powerpc/include/asm/config_mpc85xx.h
>> @@ -734,6 +734,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
>> #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
>> #define CONFIG_SYS_FSL_ERRATUM_A006261
>> #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
>> +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
>> +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
>>
>> #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
>> #define CONFIG_E6500
>> @@ -778,6 +780,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
>> #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
>> #define CONFIG_SYS_FSL_SFP_VER_3_0
>> #define CONFIG_SYS_FSL_ISBC_VER		2
>> +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
>> +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
>> +
>>
>> #elif defined(CONFIG_PPC_C29X)
>> #define CONFIG_MAX_CPUS			1
>> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
>> index 7b146a3..e888079 100644
>> --- a/drivers/mmc/fsl_esdhc.c
>> +++ b/drivers/mmc/fsl_esdhc.c
>> @@ -244,6 +244,9 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
>> 		timeout++;
>> #endif
>>
>> +#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
>> +	timeout = 0xE;
>> +#endif
>> 	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
>>
>> 	return 0;
> ----------8<-----------------
>
>> @@ -604,7 +607,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
>> 	mmc->f_min = 400000;
>> 	mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000);
>>
>> -	mmc->b_max = 0;
>> +	mmc->b_max = 0xFFFF;
>> 	mmc_register(mmc);
>>
>> 	return 0;
> ----------8<-----------------
>
> ^ This chunk is no longer needed.
>
>> -- 
>> 1.8.5
>>
>>
> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
>
>
>