From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59360) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WXs1N-0000Dx-44 for qemu-devel@nongnu.org; Wed, 09 Apr 2014 08:54:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WXs1H-0008OE-PQ for qemu-devel@nongnu.org; Wed, 09 Apr 2014 08:54:29 -0400 Received: from lhrrgout.huawei.com ([194.213.3.17]:13421) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WXs1H-0008NC-Gc for qemu-devel@nongnu.org; Wed, 09 Apr 2014 08:54:23 -0400 Message-ID: <534542E8.10006@huawei.com> Date: Wed, 9 Apr 2014 14:54:00 +0200 From: Claudio Fontana MIME-Version: 1.0 References: <1396555000-8205-1-git-send-email-rth@twiddle.net> <1396555000-8205-22-git-send-email-rth@twiddle.net> In-Reply-To: <1396555000-8205-22-git-send-email-rth@twiddle.net> Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v3 21/26] tcg-aarch64: Introduce tcg_out_insn_3507 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson , qemu-devel@nongnu.org Cc: claudio.fontana@gmail.com On 03.04.2014 21:56, Richard Henderson wrote: > Cleaning up the implementation of REV and REV16 at the same time. > > Reviewed-by: Claudio Fontana > Signed-off-by: Richard Henderson > --- > tcg/aarch64/tcg-target.c | 22 ++++++++++++++-------- > 1 file changed, 14 insertions(+), 8 deletions(-) During testing I found this patch causes a regression for big endian targets (sparc). Can you take a look? I think it might be related to the extended form of the REV instruction needing an additional 0x400. See below. > > diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c > index caaf8a2..de7490d 100644 > --- a/tcg/aarch64/tcg-target.c > +++ b/tcg/aarch64/tcg-target.c > @@ -327,6 +327,10 @@ typedef enum { > I3506_CSEL = 0x1a800000, > I3506_CSINC = 0x1a800400, > > + /* Data-processing (1 source) instructions. */ > + I3507_REV16 = 0x5ac00400, > + I3507_REV = 0x5ac00800, > + > /* Data-processing (2 source) instructions. */ > I3508_LSLV = 0x1ac02000, > I3508_LSRV = 0x1ac02400, > @@ -545,6 +549,12 @@ static void tcg_out_insn_3506(TCGContext *s, AArch64Insn insn, TCGType ext, > | tcg_cond_to_aarch64[c] << 12); > } > > +static void tcg_out_insn_3507(TCGContext *s, AArch64Insn insn, TCGType ext, > + TCGReg rd, TCGReg rn) > +{ > + tcg_out32(s, insn | ext << 31 | rn << 5 | rd); > +} > + > static void tcg_out_insn_3509(TCGContext *s, AArch64Insn insn, TCGType ext, > TCGReg rd, TCGReg rn, TCGReg rm, TCGReg ra) > { > @@ -961,19 +971,15 @@ static void tcg_out_brcond(TCGContext *s, TCGMemOp ext, TCGCond c, TCGArg a, > } > > static inline void tcg_out_rev(TCGContext *s, TCGType ext, > - TCGReg rd, TCGReg rm) > + TCGReg rd, TCGReg rn) > { > - /* using REV 0x5ac00800 */ > - unsigned int base = ext ? 0xdac00c00 : 0x5ac00800; see the extended form 0xdac00c00 <- > - tcg_out32(s, base | rm << 5 | rd); > + tcg_out_insn(s, 3507, REV, ext, rd, rn); > } > > static inline void tcg_out_rev16(TCGContext *s, TCGType ext, > - TCGReg rd, TCGReg rm) > + TCGReg rd, TCGReg rn) > { > - /* using REV16 0x5ac00400 */ > - unsigned int base = ext ? 0xdac00400 : 0x5ac00400; > - tcg_out32(s, base | rm << 5 | rd); > + tcg_out_insn(s, 3507, REV16, ext, rd, rn); while this does not have it. > } > > static inline void tcg_out_sxt(TCGContext *s, TCGType ext, TCGMemOp s_bits, > Ciao, Claudio