diff for duplicates of <5345AD00.9020508@free-electrons.com> diff --git a/a/1.txt b/N1/1.txt index cbe82f2..474e5bd 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -92,25 +92,25 @@ On 09/04/2014 19:45, Matthias Brugger wrote: > + #address-cells = <1>; > + #size-cells = <0>; > + -> + cpu at 0 { +> + cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + next-level-cache = <&L2>; > + reg = <0x0>; > + }; -> + cpu at 1 { +> + cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + next-level-cache = <&L2>; > + reg = <0x1>; > + }; -> + cpu at 2 { +> + cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + next-level-cache = <&L2>; > + reg = <0x2>; > + }; -> + cpu at 3 { +> + cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + next-level-cache = <&L2>; @@ -151,7 +151,7 @@ common framework support yet? > + clock-ranges; > + ranges; > + -> + gic: interrupt-controller at 10212000 { +> + gic: interrupt-controller@10212000 { > + compatible = "arm,cortex-a9-gic"; > + interrupt-controller; > + #interrupt-cells = <3>; @@ -159,14 +159,14 @@ common framework support yet? > + <0x10212000 0x1000>; > + }; > + -> + L2: l2-cache-controller at 1020e000 { +> + L2: l2-cache-controller@1020e000 { > + compatible = "arm,pl310-cache"; > + reg = <0x1020e000 0x1000>; > + cache-unified; > + cache-level = <2>; > + }; > + -> + timer: timer at 10008000 { +> + timer: timer@10008000 { > + compatible = "mediatek,mtk6589-timer"; > + reg = <0x10008000 0x80>; > + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>; diff --git a/a/content_digest b/N1/content_digest index e98ceb1..7ed9eed 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,9 +1,31 @@ "ref\01397072736-10793-1-git-send-email-matthias.bgg@gmail.com\0" "ref\01397072736-10793-4-git-send-email-matthias.bgg@gmail.com\0" - "From\0gregory.clement@free-electrons.com (Gregory CLEMENT)\0" - "Subject\0[PATCH 3/4] arm: add basic support for Mediatek MT6589 boards\0" + "From\0Gregory CLEMENT <gregory.clement@free-electrons.com>\0" + "Subject\0Re: [PATCH 3/4] arm: add basic support for Mediatek MT6589 boards\0" "Date\0Wed, 09 Apr 2014 20:26:40 +0000\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Matthias Brugger <matthias.bgg@gmail.com>" + " linux-kernel@vger.kernel.org\0" + "Cc\0mark.rutland@arm.com" + andrew@lunn.ch + linux-doc@vger.kernel.org + thierry.reding@gmail.com + heiko.stuebner@bq.com + linux@arm.linux.org.uk + daniel.lezcano@linaro.org + florian.vaussard@epfl.ch + sebastian.hesselbarth@gmail.com + devicetree@vger.kernel.org + jason@lakedaemon.net + pawel.moll@arm.com + ijc+devicetree@hellion.org.uk + robh+dt@kernel.org + tglx@linutronix.de + linux-arm-kernel@lists.infradead.org + rdunlap@infradead.org + silvio.fricke@gmail.com + galak@codeaurora.org + olof@lixom.net + " jic23@kernel.org\0" "\00:1\0" "b\0" "Hi Matthias,\n" @@ -100,25 +122,25 @@ "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu at 0 {\n" + "> +\t\tcpu@0 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tnext-level-cache = <&L2>;\n" "> +\t\t\treg = <0x0>;\n" "> +\t\t};\n" - "> +\t\tcpu at 1 {\n" + "> +\t\tcpu@1 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tnext-level-cache = <&L2>;\n" "> +\t\t\treg = <0x1>;\n" "> +\t\t};\n" - "> +\t\tcpu at 2 {\n" + "> +\t\tcpu@2 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tnext-level-cache = <&L2>;\n" "> +\t\t\treg = <0x2>;\n" "> +\t\t};\n" - "> +\t\tcpu at 3 {\n" + "> +\t\tcpu@3 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\tnext-level-cache = <&L2>;\n" @@ -159,7 +181,7 @@ "> +\t\tclock-ranges;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tgic: interrupt-controller at 10212000 {\n" + "> +\t\tgic: interrupt-controller@10212000 {\n" "> +\t\t\tcompatible = \"arm,cortex-a9-gic\";\n" "> +\t\t\tinterrupt-controller;\n" "> +\t\t\t#interrupt-cells = <3>;\n" @@ -167,14 +189,14 @@ "> +\t\t\t <0x10212000 0x1000>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tL2: l2-cache-controller at 1020e000 {\n" + "> +\t\tL2: l2-cache-controller@1020e000 {\n" "> +\t\t\tcompatible = \"arm,pl310-cache\";\n" "> +\t\t\treg = <0x1020e000 0x1000>;\n" "> +\t\t\tcache-unified;\n" "> +\t\t\tcache-level = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\ttimer: timer at 10008000 {\n" + "> +\t\ttimer: timer@10008000 {\n" "> +\t\t\tcompatible = \"mediatek,mtk6589-timer\";\n" "> +\t\t\treg = <0x10008000 0x80>;\n" "> +\t\t\tinterrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;\n" @@ -281,4 +303,4 @@ "development, consulting, training and support.\n" http://free-electrons.com -ba3fb34f6f17851c551a03369fd5c143832a69bb764986c06ea7f1586cc904a6 +b15996bd37f76954053632be12ba27556285a1c82fe93253831921ea9863509f
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