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diff for duplicates of <53465A4B.4040906@free-electrons.com>

diff --git a/a/1.txt b/N1/1.txt
index 966693c..7f6331a 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -94,25 +94,25 @@ On 10/04/2014 08:29, Matthias Brugger wrote:
 >>> +             #address-cells = <1>;
 >>> +             #size-cells = <0>;
 >>> +
->>> +             cpu at 0 {
+>>> +             cpu@0 {
 >>> +                     device_type = "cpu";
 >>> +                     compatible = "arm,cortex-a7";
 >>> +                     next-level-cache = <&L2>;
 >>> +                     reg = <0x0>;
 >>> +             };
->>> +             cpu at 1 {
+>>> +             cpu@1 {
 >>> +                     device_type = "cpu";
 >>> +                     compatible = "arm,cortex-a7";
 >>> +                     next-level-cache = <&L2>;
 >>> +                     reg = <0x1>;
 >>> +             };
->>> +             cpu at 2 {
+>>> +             cpu@2 {
 >>> +                     device_type = "cpu";
 >>> +                     compatible = "arm,cortex-a7";
 >>> +                     next-level-cache = <&L2>;
 >>> +                     reg = <0x2>;
 >>> +             };
->>> +             cpu at 3 {
+>>> +             cpu@3 {
 >>> +                     device_type = "cpu";
 >>> +                     compatible = "arm,cortex-a7";
 >>> +                     next-level-cache = <&L2>;
@@ -168,7 +168,7 @@ Gregory
 >>> +             clock-ranges;
 >>> +             ranges;
 >>> +
->>> +             gic: interrupt-controller at 10212000 {
+>>> +             gic: interrupt-controller@10212000 {
 >>> +                     compatible = "arm,cortex-a9-gic";
 >>> +                     interrupt-controller;
 >>> +                     #interrupt-cells = <3>;
@@ -176,14 +176,14 @@ Gregory
 >>> +                           <0x10212000 0x1000>;
 >>> +             };
 >>> +
->>> +             L2: l2-cache-controller at 1020e000 {
+>>> +             L2: l2-cache-controller@1020e000 {
 >>> +                     compatible = "arm,pl310-cache";
 >>> +                     reg = <0x1020e000 0x1000>;
 >>> +                     cache-unified;
 >>> +                     cache-level = <2>;
 >>> +             };
 >>> +
->>> +             timer: timer at 10008000 {
+>>> +             timer: timer@10008000 {
 >>> +                     compatible = "mediatek,mtk6589-timer";
 >>> +                     reg = <0x10008000 0x80>;
 >>> +                     interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
diff --git a/a/content_digest b/N1/content_digest
index 84edd2b..9f2559f 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -2,10 +2,29 @@
  "ref\01397072736-10793-4-git-send-email-matthias.bgg@gmail.com\0"
  "ref\05345AD00.9020508@free-electrons.com\0"
  "ref\0CABuKBeKnEw38sQYwrkheoWetZZcPTJhKRsBK4a62FS6-6dRFTA@mail.gmail.com\0"
- "From\0gregory.clement@free-electrons.com (Gregory CLEMENT)\0"
- "Subject\0[PATCH 3/4] arm: add basic support for Mediatek MT6589 boards\0"
+ "From\0Gregory CLEMENT <gregory.clement@free-electrons.com>\0"
+ "Subject\0Re: [PATCH 3/4] arm: add basic support for Mediatek MT6589 boards\0"
  "Date\0Thu, 10 Apr 2014 08:46:03 +0000\0"
- "To\0linux-arm-kernel@lists.infradead.org\0"
+ "To\0Matthias Brugger <matthias.bgg@gmail.com>\0"
+ "Cc\0linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>"
+  Mark Rutland <mark.rutland@arm.com>
+  Andrew Lunn <andrew@lunn.ch>
+  linux-doc@vger.kernel.org <linux-doc@vger.kernel.org>
+  Thierry Reding <thierry.reding@gmail.com>
+ " Heiko St\303\274bner <heiko.stuebner@bq.com>"
+  Russell King <linux@arm.linux.org.uk>
+  Daniel Lezcano <daniel.lezcano@linaro.org>
+  Florian Vaussard <florian.vaussard@epfl.ch>
+  Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+  devicetree@vger.kernel.org <devicetree@vger.kernel.org>
+  Jason Cooper <jason@lakedaemon.net>
+  Pawel Moll <pawel.moll@arm.com>
+  Ian Campbell <ijc+devicetree@hellion.org.uk>
+  Rob Herring <robh+dt@kernel.org>
+  Thomas Gleixner <tglx@linutronix.de>
+  linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>
+  Randy Dunlap <rdunlap@infradead.org>
+ " Silvio F <silvio.fricke@gmail.com>\0"
  "\00:1\0"
  "b\0"
  "On 10/04/2014 08:29, Matthias Brugger wrote:\n"
@@ -104,25 +123,25 @@
  ">>> +             #address-cells = <1>;\n"
  ">>> +             #size-cells = <0>;\n"
  ">>> +\n"
- ">>> +             cpu at 0 {\n"
+ ">>> +             cpu@0 {\n"
  ">>> +                     device_type = \"cpu\";\n"
  ">>> +                     compatible = \"arm,cortex-a7\";\n"
  ">>> +                     next-level-cache = <&L2>;\n"
  ">>> +                     reg = <0x0>;\n"
  ">>> +             };\n"
- ">>> +             cpu at 1 {\n"
+ ">>> +             cpu@1 {\n"
  ">>> +                     device_type = \"cpu\";\n"
  ">>> +                     compatible = \"arm,cortex-a7\";\n"
  ">>> +                     next-level-cache = <&L2>;\n"
  ">>> +                     reg = <0x1>;\n"
  ">>> +             };\n"
- ">>> +             cpu at 2 {\n"
+ ">>> +             cpu@2 {\n"
  ">>> +                     device_type = \"cpu\";\n"
  ">>> +                     compatible = \"arm,cortex-a7\";\n"
  ">>> +                     next-level-cache = <&L2>;\n"
  ">>> +                     reg = <0x2>;\n"
  ">>> +             };\n"
- ">>> +             cpu at 3 {\n"
+ ">>> +             cpu@3 {\n"
  ">>> +                     device_type = \"cpu\";\n"
  ">>> +                     compatible = \"arm,cortex-a7\";\n"
  ">>> +                     next-level-cache = <&L2>;\n"
@@ -178,7 +197,7 @@
  ">>> +             clock-ranges;\n"
  ">>> +             ranges;\n"
  ">>> +\n"
- ">>> +             gic: interrupt-controller at 10212000 {\n"
+ ">>> +             gic: interrupt-controller@10212000 {\n"
  ">>> +                     compatible = \"arm,cortex-a9-gic\";\n"
  ">>> +                     interrupt-controller;\n"
  ">>> +                     #interrupt-cells = <3>;\n"
@@ -186,14 +205,14 @@
  ">>> +                           <0x10212000 0x1000>;\n"
  ">>> +             };\n"
  ">>> +\n"
- ">>> +             L2: l2-cache-controller at 1020e000 {\n"
+ ">>> +             L2: l2-cache-controller@1020e000 {\n"
  ">>> +                     compatible = \"arm,pl310-cache\";\n"
  ">>> +                     reg = <0x1020e000 0x1000>;\n"
  ">>> +                     cache-unified;\n"
  ">>> +                     cache-level = <2>;\n"
  ">>> +             };\n"
  ">>> +\n"
- ">>> +             timer: timer at 10008000 {\n"
+ ">>> +             timer: timer@10008000 {\n"
  ">>> +                     compatible = \"mediatek,mtk6589-timer\";\n"
  ">>> +                     reg = <0x10008000 0x80>;\n"
  ">>> +                     interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;\n"
@@ -310,4 +329,4 @@
  "development, consulting, training and support.\n"
  http://free-electrons.com
 
-1f2fc6d10192fb75f4d9e9f8c2132b60a7b682984c04fec6fddcd250c687e596
+c677546ad4be12697bbfbaf8da522f930b06af2ff1835d08f3b81a6261f9514c

diff --git a/a/1.txt b/N2/1.txt
index 966693c..7f6331a 100644
--- a/a/1.txt
+++ b/N2/1.txt
@@ -94,25 +94,25 @@ On 10/04/2014 08:29, Matthias Brugger wrote:
 >>> +             #address-cells = <1>;
 >>> +             #size-cells = <0>;
 >>> +
->>> +             cpu at 0 {
+>>> +             cpu@0 {
 >>> +                     device_type = "cpu";
 >>> +                     compatible = "arm,cortex-a7";
 >>> +                     next-level-cache = <&L2>;
 >>> +                     reg = <0x0>;
 >>> +             };
->>> +             cpu at 1 {
+>>> +             cpu@1 {
 >>> +                     device_type = "cpu";
 >>> +                     compatible = "arm,cortex-a7";
 >>> +                     next-level-cache = <&L2>;
 >>> +                     reg = <0x1>;
 >>> +             };
->>> +             cpu at 2 {
+>>> +             cpu@2 {
 >>> +                     device_type = "cpu";
 >>> +                     compatible = "arm,cortex-a7";
 >>> +                     next-level-cache = <&L2>;
 >>> +                     reg = <0x2>;
 >>> +             };
->>> +             cpu at 3 {
+>>> +             cpu@3 {
 >>> +                     device_type = "cpu";
 >>> +                     compatible = "arm,cortex-a7";
 >>> +                     next-level-cache = <&L2>;
@@ -168,7 +168,7 @@ Gregory
 >>> +             clock-ranges;
 >>> +             ranges;
 >>> +
->>> +             gic: interrupt-controller at 10212000 {
+>>> +             gic: interrupt-controller@10212000 {
 >>> +                     compatible = "arm,cortex-a9-gic";
 >>> +                     interrupt-controller;
 >>> +                     #interrupt-cells = <3>;
@@ -176,14 +176,14 @@ Gregory
 >>> +                           <0x10212000 0x1000>;
 >>> +             };
 >>> +
->>> +             L2: l2-cache-controller at 1020e000 {
+>>> +             L2: l2-cache-controller@1020e000 {
 >>> +                     compatible = "arm,pl310-cache";
 >>> +                     reg = <0x1020e000 0x1000>;
 >>> +                     cache-unified;
 >>> +                     cache-level = <2>;
 >>> +             };
 >>> +
->>> +             timer: timer at 10008000 {
+>>> +             timer: timer@10008000 {
 >>> +                     compatible = "mediatek,mtk6589-timer";
 >>> +                     reg = <0x10008000 0x80>;
 >>> +                     interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
diff --git a/a/content_digest b/N2/content_digest
index 84edd2b..c94ceb3 100644
--- a/a/content_digest
+++ b/N2/content_digest
@@ -2,10 +2,32 @@
  "ref\01397072736-10793-4-git-send-email-matthias.bgg@gmail.com\0"
  "ref\05345AD00.9020508@free-electrons.com\0"
  "ref\0CABuKBeKnEw38sQYwrkheoWetZZcPTJhKRsBK4a62FS6-6dRFTA@mail.gmail.com\0"
- "From\0gregory.clement@free-electrons.com (Gregory CLEMENT)\0"
- "Subject\0[PATCH 3/4] arm: add basic support for Mediatek MT6589 boards\0"
+ "From\0Gregory CLEMENT <gregory.clement@free-electrons.com>\0"
+ "Subject\0Re: [PATCH 3/4] arm: add basic support for Mediatek MT6589 boards\0"
  "Date\0Thu, 10 Apr 2014 08:46:03 +0000\0"
- "To\0linux-arm-kernel@lists.infradead.org\0"
+ "To\0Matthias Brugger <matthias.bgg@gmail.com>\0"
+ "Cc\0linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>"
+  Mark Rutland <mark.rutland@arm.com>
+  Andrew Lunn <andrew@lunn.ch>
+  linux-doc@vger.kernel.org <linux-doc@vger.kernel.org>
+  Thierry Reding <thierry.reding@gmail.com>
+ " Heiko St\303\274bner <heiko.stuebner@bq.com>"
+  Russell King <linux@arm.linux.org.uk>
+  Daniel Lezcano <daniel.lezcano@linaro.org>
+  Florian Vaussard <florian.vaussard@epfl.ch>
+  Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+  devicetree@vger.kernel.org <devicetree@vger.kernel.org>
+  Jason Cooper <jason@lakedaemon.net>
+  Pawel Moll <pawel.moll@arm.com>
+  Ian Campbell <ijc+devicetree@hellion.org.uk>
+  Rob Herring <robh+dt@kernel.org>
+  Thomas Gleixner <tglx@linutronix.de>
+  linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>
+  Randy Dunlap <rdunlap@infradead.org>
+  Silvio F <silvio.fricke@gmail.com>
+  Kumar Gala <galak@codeaurora.org>
+  Olof Johansson <olof@lixom.net>
+ " Jonathan Cameron <jic23@kernel.org>\0"
  "\00:1\0"
  "b\0"
  "On 10/04/2014 08:29, Matthias Brugger wrote:\n"
@@ -104,25 +126,25 @@
  ">>> +             #address-cells = <1>;\n"
  ">>> +             #size-cells = <0>;\n"
  ">>> +\n"
- ">>> +             cpu at 0 {\n"
+ ">>> +             cpu@0 {\n"
  ">>> +                     device_type = \"cpu\";\n"
  ">>> +                     compatible = \"arm,cortex-a7\";\n"
  ">>> +                     next-level-cache = <&L2>;\n"
  ">>> +                     reg = <0x0>;\n"
  ">>> +             };\n"
- ">>> +             cpu at 1 {\n"
+ ">>> +             cpu@1 {\n"
  ">>> +                     device_type = \"cpu\";\n"
  ">>> +                     compatible = \"arm,cortex-a7\";\n"
  ">>> +                     next-level-cache = <&L2>;\n"
  ">>> +                     reg = <0x1>;\n"
  ">>> +             };\n"
- ">>> +             cpu at 2 {\n"
+ ">>> +             cpu@2 {\n"
  ">>> +                     device_type = \"cpu\";\n"
  ">>> +                     compatible = \"arm,cortex-a7\";\n"
  ">>> +                     next-level-cache = <&L2>;\n"
  ">>> +                     reg = <0x2>;\n"
  ">>> +             };\n"
- ">>> +             cpu at 3 {\n"
+ ">>> +             cpu@3 {\n"
  ">>> +                     device_type = \"cpu\";\n"
  ">>> +                     compatible = \"arm,cortex-a7\";\n"
  ">>> +                     next-level-cache = <&L2>;\n"
@@ -178,7 +200,7 @@
  ">>> +             clock-ranges;\n"
  ">>> +             ranges;\n"
  ">>> +\n"
- ">>> +             gic: interrupt-controller at 10212000 {\n"
+ ">>> +             gic: interrupt-controller@10212000 {\n"
  ">>> +                     compatible = \"arm,cortex-a9-gic\";\n"
  ">>> +                     interrupt-controller;\n"
  ">>> +                     #interrupt-cells = <3>;\n"
@@ -186,14 +208,14 @@
  ">>> +                           <0x10212000 0x1000>;\n"
  ">>> +             };\n"
  ">>> +\n"
- ">>> +             L2: l2-cache-controller at 1020e000 {\n"
+ ">>> +             L2: l2-cache-controller@1020e000 {\n"
  ">>> +                     compatible = \"arm,pl310-cache\";\n"
  ">>> +                     reg = <0x1020e000 0x1000>;\n"
  ">>> +                     cache-unified;\n"
  ">>> +                     cache-level = <2>;\n"
  ">>> +             };\n"
  ">>> +\n"
- ">>> +             timer: timer at 10008000 {\n"
+ ">>> +             timer: timer@10008000 {\n"
  ">>> +                     compatible = \"mediatek,mtk6589-timer\";\n"
  ">>> +                     reg = <0x10008000 0x80>;\n"
  ">>> +                     interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;\n"
@@ -310,4 +332,4 @@
  "development, consulting, training and support.\n"
  http://free-electrons.com
 
-1f2fc6d10192fb75f4d9e9f8c2132b60a7b682984c04fec6fddcd250c687e596
+c869115e827b01e6f04b1a5601e61e62208ecc9342c5c9081b0104a8589ad8dd

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