diff for duplicates of <5347AC8A.7090006@samsung.com> diff --git a/a/1.txt b/N1/1.txt index b3cf0a1..9bde74f 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -56,3 +56,10 @@ series. Best regards, Tomasz +-------------- next part -------------- +A non-text attachment was scrubbed... +Name: 0001-ARM-EXYNOS-Move-arm-core-power-down-clock-to-exynos5.patch +Type: text/x-patch +Size: 6226 bytes +Desc: not available +URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140411/1ad9e7d6/attachment.bin> diff --git a/a/2.hdr b/a/2.hdr deleted file mode 100644 index a617da5..0000000 --- a/a/2.hdr +++ /dev/null @@ -1,6 +0,0 @@ -Content-Type: text/x-patch; - name="0001-ARM-EXYNOS-Move-arm-core-power-down-clock-to-exynos5.patch" -Content-Transfer-Encoding: 7bit -Content-Disposition: attachment; - filename*0="0001-ARM-EXYNOS-Move-arm-core-power-down-clock-to-exynos5.pa"; - filename*1="tch" diff --git a/a/2.txt b/a/2.txt deleted file mode 100644 index 0c09deb..0000000 --- a/a/2.txt +++ /dev/null @@ -1,182 +0,0 @@ ->From 31d02976c517c1e8d00a0c1296e5fa132af78880 Mon Sep 17 00:00:00 2001 -From: Amit Daniel Kachhap <amit.daniel@samsung.com> -Date: Fri, 11 Oct 2013 11:12:14 +0530 -Subject: [PATCH] ARM: EXYNOS: Move arm core power down clock to exynos5250 - common clock - -Now with common clock support added for exynos5250 it is necessary to move -this code to exynos5250 common clock driver as clock registers should be -handled there. This change is tested in exynos5250 based arndale platform. - -Cc: Abhilash Kesavan <a.kesavan@samsung.com> -Cc: Thomas Abraham <thomas.abraham@linaro.org> -Acked-by: Kukjin Kim <kgene.kim@samsugn.com> -Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> -Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com> -[t.figa: Rebased onto current kernel sources.] -Signed-off-by: Tomasz Figa <t.figa@samsung.com> ---- - arch/arm/mach-exynos/cpuidle.c | 54 ------------------------------------ - drivers/clk/samsung/clk-exynos5250.c | 42 ++++++++++++++++++++++++++++ - 2 files changed, 42 insertions(+), 54 deletions(-) - -diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c -index c57cae0..8125a15 100644 ---- a/arch/arm/mach-exynos/cpuidle.c -+++ b/arch/arm/mach-exynos/cpuidle.c -@@ -41,25 +41,6 @@ - - #define S5P_CHECK_AFTR 0xFCBA0D10 - --#define EXYNOS5_PWR_CTRL1 (S5P_VA_CMU + 0x01020) --#define EXYNOS5_PWR_CTRL2 (S5P_VA_CMU + 0x01024) -- --#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28) --#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16) --#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) --#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8) --#define PWR_CTRL1_USE_CORE1_WFE (1 << 5) --#define PWR_CTRL1_USE_CORE0_WFE (1 << 4) --#define PWR_CTRL1_USE_CORE1_WFI (1 << 1) --#define PWR_CTRL1_USE_CORE0_WFI (1 << 0) -- --#define PWR_CTRL2_DIV2_UP_EN (1 << 25) --#define PWR_CTRL2_DIV1_UP_EN (1 << 24) --#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16) --#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8) --#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4) --#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0) -- - static int exynos4_enter_lowpower(struct cpuidle_device *dev, - struct cpuidle_driver *drv, - int index); -@@ -182,46 +163,11 @@ static int exynos4_enter_lowpower(struct cpuidle_device *dev, - return exynos4_enter_core0_aftr(dev, drv, new_index); - } - --static void __init exynos5_core_down_clk(void) --{ -- unsigned int tmp; -- -- /* -- * Enable arm clock down (in idle) and set arm divider -- * ratios in WFI/WFE state. -- */ -- tmp = PWR_CTRL1_CORE2_DOWN_RATIO | \ -- PWR_CTRL1_CORE1_DOWN_RATIO | \ -- PWR_CTRL1_DIV2_DOWN_EN | \ -- PWR_CTRL1_DIV1_DOWN_EN | \ -- PWR_CTRL1_USE_CORE1_WFE | \ -- PWR_CTRL1_USE_CORE0_WFE | \ -- PWR_CTRL1_USE_CORE1_WFI | \ -- PWR_CTRL1_USE_CORE0_WFI; -- __raw_writel(tmp, EXYNOS5_PWR_CTRL1); -- -- /* -- * Enable arm clock up (on exiting idle). Set arm divider -- * ratios when not in idle along with the standby duration -- * ratios. -- */ -- tmp = PWR_CTRL2_DIV2_UP_EN | \ -- PWR_CTRL2_DIV1_UP_EN | \ -- PWR_CTRL2_DUR_STANDBY2_VAL | \ -- PWR_CTRL2_DUR_STANDBY1_VAL | \ -- PWR_CTRL2_CORE2_UP_RATIO | \ -- PWR_CTRL2_CORE1_UP_RATIO; -- __raw_writel(tmp, EXYNOS5_PWR_CTRL2); --} -- - static int exynos_cpuidle_probe(struct platform_device *pdev) - { - int cpu_id, ret; - struct cpuidle_device *device; - -- if (soc_is_exynos5250()) -- exynos5_core_down_clk(); -- - if (soc_is_exynos5440()) - exynos4_idle_driver.state_count = 1; - -diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c -index e7ee442..2bb4625 100644 ---- a/drivers/clk/samsung/clk-exynos5250.c -+++ b/drivers/clk/samsung/clk-exynos5250.c -@@ -24,6 +24,8 @@ - #define APLL_CON0 0x100 - #define SRC_CPU 0x200 - #define DIV_CPU0 0x500 -+#define PWR_CTRL1 0x1020 -+#define PWR_CTRL2 0x1024 - #define MPLL_LOCK 0x4000 - #define MPLL_CON0 0x4100 - #define SRC_CORE1 0x4204 -@@ -80,6 +82,23 @@ - #define SRC_CDREX 0x20200 - #define PLL_DIV2_SEL 0x20a24 - -+/*Below definitions are used for PWR_CTRL settings*/ -+#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28) -+#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16) -+#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) -+#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8) -+#define PWR_CTRL1_USE_CORE1_WFE (1 << 5) -+#define PWR_CTRL1_USE_CORE0_WFE (1 << 4) -+#define PWR_CTRL1_USE_CORE1_WFI (1 << 1) -+#define PWR_CTRL1_USE_CORE0_WFI (1 << 0) -+ -+#define PWR_CTRL2_DIV2_UP_EN (1 << 25) -+#define PWR_CTRL2_DIV1_UP_EN (1 << 24) -+#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16) -+#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8) -+#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4) -+#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0) -+ - /* list of PLLs to be registered */ - enum exynos5250_plls { - apll, mpll, cpll, epll, vpll, gpll, bpll, -@@ -98,6 +117,8 @@ static struct samsung_clk_reg_dump *exynos5250_save; - static unsigned long exynos5250_clk_regs[] __initdata = { - SRC_CPU, - DIV_CPU0, -+ PWR_CTRL1, -+ PWR_CTRL2, - SRC_CORE1, - SRC_TOP0, - SRC_TOP2, -@@ -686,6 +707,7 @@ static struct of_device_id ext_clk_match[] __initdata = { - /* register exynox5250 clocks */ - static void __init exynos5250_clk_init(struct device_node *np) - { -+ unsigned int tmp; - if (np) { - reg_base = of_iomap(np, 0); - if (!reg_base) -@@ -722,6 +744,26 @@ static void __init exynos5250_clk_init(struct device_node *np) - samsung_clk_register_gate(exynos5250_gate_clks, - ARRAY_SIZE(exynos5250_gate_clks)); - -+ /* -+ * Enable arm clock down (in idle) and set arm divider -+ * ratios in WFI/WFE state. -+ */ -+ tmp = (PWR_CTRL1_CORE2_DOWN_RATIO | PWR_CTRL1_CORE1_DOWN_RATIO | -+ PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN | -+ PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE | -+ PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI); -+ __raw_writel(tmp, reg_base + PWR_CTRL1); -+ -+ /* -+ * Enable arm clock up (on exiting idle). Set arm divider -+ * ratios when not in idle along with the standby duration -+ * ratios. -+ */ -+ tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN | -+ PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL | -+ PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO); -+ __raw_writel(tmp, reg_base + PWR_CTRL2); -+ - exynos5250_clk_sleep_init(); - - pr_info("Exynos5250: clock setup completed, armclk=%ld\n", --- -1.9.1 diff --git a/a/content_digest b/N1/content_digest index f9c8af9..3d86653 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -4,19 +4,11 @@ "ref\05346A958.1030302@linaro.org\0" "ref\05346BA09.9020708@samsung.com\0" "ref\05347A816.4020609@linaro.org\0" - "From\0Tomasz Figa <t.figa@samsung.com>\0" - "Subject\0Re: [PATCH V4 10/20] ARM: exynos: cpuidle: Move clock setup to pm.c\0" + "From\0t.figa@samsung.com (Tomasz Figa)\0" + "Subject\0[PATCH V4 10/20] ARM: exynos: cpuidle: Move clock setup to pm.c\0" "Date\0Fri, 11 Apr 2014 10:49:14 +0200\0" - "To\0Daniel Lezcano <daniel.lezcano@linaro.org>" - " kgene.kim@samsung.com\0" - "Cc\0linux-arm-kernel@lists.infradead.org" - linux-samsung-soc@vger.kernel.org - linaro-kernel@lists.linaro.org - b.zolnierkie@samsung.com - sachin.kamat@linaro.org - viresh.kumar@linaro.org - " rjw@rjwysocki.net\0" - "\01:1\0" + "To\0linux-arm-kernel@lists.infradead.org\0" + "\00:1\0" "b\0" "On 11.04.2014 10:30, Daniel Lezcano wrote:\n" "> On 04/10/2014 05:34 PM, Tomasz Figa wrote:\n" @@ -75,191 +67,13 @@ "series.\n" "\n" "Best regards,\n" - Tomasz - "\01:2\0" - "fn\00001-ARM-EXYNOS-Move-arm-core-power-down-clock-to-exynos5.patch\0" - "b\0" - ">From 31d02976c517c1e8d00a0c1296e5fa132af78880 Mon Sep 17 00:00:00 2001\n" - "From: Amit Daniel Kachhap <amit.daniel@samsung.com>\n" - "Date: Fri, 11 Oct 2013 11:12:14 +0530\n" - "Subject: [PATCH] ARM: EXYNOS: Move arm core power down clock to exynos5250\n" - " common clock\n" - "\n" - "Now with common clock support added for exynos5250 it is necessary to move\n" - "this code to exynos5250 common clock driver as clock registers should be\n" - "handled there. This change is tested in exynos5250 based arndale platform.\n" - "\n" - "Cc: Abhilash Kesavan <a.kesavan@samsung.com>\n" - "Cc: Thomas Abraham <thomas.abraham@linaro.org>\n" - "Acked-by: Kukjin Kim <kgene.kim@samsugn.com>\n" - "Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>\n" - "Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>\n" - "[t.figa: Rebased onto current kernel sources.]\n" - "Signed-off-by: Tomasz Figa <t.figa@samsung.com>\n" - "---\n" - " arch/arm/mach-exynos/cpuidle.c | 54 ------------------------------------\n" - " drivers/clk/samsung/clk-exynos5250.c | 42 ++++++++++++++++++++++++++++\n" - " 2 files changed, 42 insertions(+), 54 deletions(-)\n" - "\n" - "diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c\n" - "index c57cae0..8125a15 100644\n" - "--- a/arch/arm/mach-exynos/cpuidle.c\n" - "+++ b/arch/arm/mach-exynos/cpuidle.c\n" - "@@ -41,25 +41,6 @@\n" - " \n" - " #define S5P_CHECK_AFTR\t\t0xFCBA0D10\n" - " \n" - "-#define EXYNOS5_PWR_CTRL1\t\t\t(S5P_VA_CMU + 0x01020)\n" - "-#define EXYNOS5_PWR_CTRL2\t\t\t(S5P_VA_CMU + 0x01024)\n" - "-\n" - "-#define PWR_CTRL1_CORE2_DOWN_RATIO\t\t(7 << 28)\n" - "-#define PWR_CTRL1_CORE1_DOWN_RATIO\t\t(7 << 16)\n" - "-#define PWR_CTRL1_DIV2_DOWN_EN\t\t\t(1 << 9)\n" - "-#define PWR_CTRL1_DIV1_DOWN_EN\t\t\t(1 << 8)\n" - "-#define PWR_CTRL1_USE_CORE1_WFE\t\t\t(1 << 5)\n" - "-#define PWR_CTRL1_USE_CORE0_WFE\t\t\t(1 << 4)\n" - "-#define PWR_CTRL1_USE_CORE1_WFI\t\t\t(1 << 1)\n" - "-#define PWR_CTRL1_USE_CORE0_WFI\t\t\t(1 << 0)\n" - "-\n" - "-#define PWR_CTRL2_DIV2_UP_EN\t\t\t(1 << 25)\n" - "-#define PWR_CTRL2_DIV1_UP_EN\t\t\t(1 << 24)\n" - "-#define PWR_CTRL2_DUR_STANDBY2_VAL\t\t(1 << 16)\n" - "-#define PWR_CTRL2_DUR_STANDBY1_VAL\t\t(1 << 8)\n" - "-#define PWR_CTRL2_CORE2_UP_RATIO\t\t(1 << 4)\n" - "-#define PWR_CTRL2_CORE1_UP_RATIO\t\t(1 << 0)\n" - "-\n" - " static int exynos4_enter_lowpower(struct cpuidle_device *dev,\n" - " \t\t\t\tstruct cpuidle_driver *drv,\n" - " \t\t\t\tint index);\n" - "@@ -182,46 +163,11 @@ static int exynos4_enter_lowpower(struct cpuidle_device *dev,\n" - " \t\treturn exynos4_enter_core0_aftr(dev, drv, new_index);\n" - " }\n" - " \n" - "-static void __init exynos5_core_down_clk(void)\n" - "-{\n" - "-\tunsigned int tmp;\n" - "-\n" - "-\t/*\n" - "-\t * Enable arm clock down (in idle) and set arm divider\n" - "-\t * ratios in WFI/WFE state.\n" - "-\t */\n" - "-\ttmp = PWR_CTRL1_CORE2_DOWN_RATIO | \\\n" - "-\t PWR_CTRL1_CORE1_DOWN_RATIO | \\\n" - "-\t PWR_CTRL1_DIV2_DOWN_EN\t | \\\n" - "-\t PWR_CTRL1_DIV1_DOWN_EN\t | \\\n" - "-\t PWR_CTRL1_USE_CORE1_WFE\t | \\\n" - "-\t PWR_CTRL1_USE_CORE0_WFE\t | \\\n" - "-\t PWR_CTRL1_USE_CORE1_WFI\t | \\\n" - "-\t PWR_CTRL1_USE_CORE0_WFI;\n" - "-\t__raw_writel(tmp, EXYNOS5_PWR_CTRL1);\n" - "-\n" - "-\t/*\n" - "-\t * Enable arm clock up (on exiting idle). Set arm divider\n" - "-\t * ratios when not in idle along with the standby duration\n" - "-\t * ratios.\n" - "-\t */\n" - "-\ttmp = PWR_CTRL2_DIV2_UP_EN\t | \\\n" - "-\t PWR_CTRL2_DIV1_UP_EN\t | \\\n" - "-\t PWR_CTRL2_DUR_STANDBY2_VAL | \\\n" - "-\t PWR_CTRL2_DUR_STANDBY1_VAL | \\\n" - "-\t PWR_CTRL2_CORE2_UP_RATIO\t | \\\n" - "-\t PWR_CTRL2_CORE1_UP_RATIO;\n" - "-\t__raw_writel(tmp, EXYNOS5_PWR_CTRL2);\n" - "-}\n" - "-\n" - " static int exynos_cpuidle_probe(struct platform_device *pdev)\n" - " {\n" - " \tint cpu_id, ret;\n" - " \tstruct cpuidle_device *device;\n" - " \n" - "-\tif (soc_is_exynos5250())\n" - "-\t\texynos5_core_down_clk();\n" - "-\n" - " \tif (soc_is_exynos5440())\n" - " \t\texynos4_idle_driver.state_count = 1;\n" - " \n" - "diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c\n" - "index e7ee442..2bb4625 100644\n" - "--- a/drivers/clk/samsung/clk-exynos5250.c\n" - "+++ b/drivers/clk/samsung/clk-exynos5250.c\n" - "@@ -24,6 +24,8 @@\n" - " #define APLL_CON0\t\t0x100\n" - " #define SRC_CPU\t\t\t0x200\n" - " #define DIV_CPU0\t\t0x500\n" - "+#define PWR_CTRL1\t\t0x1020\n" - "+#define PWR_CTRL2\t\t0x1024\n" - " #define MPLL_LOCK\t\t0x4000\n" - " #define MPLL_CON0\t\t0x4100\n" - " #define SRC_CORE1\t\t0x4204\n" - "@@ -80,6 +82,23 @@\n" - " #define SRC_CDREX\t\t0x20200\n" - " #define PLL_DIV2_SEL\t\t0x20a24\n" - " \n" - "+/*Below definitions are used for PWR_CTRL settings*/\n" - "+#define PWR_CTRL1_CORE2_DOWN_RATIO\t\t(7 << 28)\n" - "+#define PWR_CTRL1_CORE1_DOWN_RATIO\t\t(7 << 16)\n" - "+#define PWR_CTRL1_DIV2_DOWN_EN\t\t\t(1 << 9)\n" - "+#define PWR_CTRL1_DIV1_DOWN_EN\t\t\t(1 << 8)\n" - "+#define PWR_CTRL1_USE_CORE1_WFE\t\t\t(1 << 5)\n" - "+#define PWR_CTRL1_USE_CORE0_WFE\t\t\t(1 << 4)\n" - "+#define PWR_CTRL1_USE_CORE1_WFI\t\t\t(1 << 1)\n" - "+#define PWR_CTRL1_USE_CORE0_WFI\t\t\t(1 << 0)\n" - "+\n" - "+#define PWR_CTRL2_DIV2_UP_EN\t\t\t(1 << 25)\n" - "+#define PWR_CTRL2_DIV1_UP_EN\t\t\t(1 << 24)\n" - "+#define PWR_CTRL2_DUR_STANDBY2_VAL\t\t(1 << 16)\n" - "+#define PWR_CTRL2_DUR_STANDBY1_VAL\t\t(1 << 8)\n" - "+#define PWR_CTRL2_CORE2_UP_RATIO\t\t(1 << 4)\n" - "+#define PWR_CTRL2_CORE1_UP_RATIO\t\t(1 << 0)\n" - "+\n" - " /* list of PLLs to be registered */\n" - " enum exynos5250_plls {\n" - " \tapll, mpll, cpll, epll, vpll, gpll, bpll,\n" - "@@ -98,6 +117,8 @@ static struct samsung_clk_reg_dump *exynos5250_save;\n" - " static unsigned long exynos5250_clk_regs[] __initdata = {\n" - " \tSRC_CPU,\n" - " \tDIV_CPU0,\n" - "+\tPWR_CTRL1,\n" - "+\tPWR_CTRL2,\n" - " \tSRC_CORE1,\n" - " \tSRC_TOP0,\n" - " \tSRC_TOP2,\n" - "@@ -686,6 +707,7 @@ static struct of_device_id ext_clk_match[] __initdata = {\n" - " /* register exynox5250 clocks */\n" - " static void __init exynos5250_clk_init(struct device_node *np)\n" - " {\n" - "+\tunsigned int tmp;\n" - " \tif (np) {\n" - " \t\treg_base = of_iomap(np, 0);\n" - " \t\tif (!reg_base)\n" - "@@ -722,6 +744,26 @@ static void __init exynos5250_clk_init(struct device_node *np)\n" - " \tsamsung_clk_register_gate(exynos5250_gate_clks,\n" - " \t\t\tARRAY_SIZE(exynos5250_gate_clks));\n" - " \n" - "+\t/*\n" - "+\t * Enable arm clock down (in idle) and set arm divider\n" - "+\t * ratios in WFI/WFE state.\n" - "+\t */\n" - "+\ttmp = (PWR_CTRL1_CORE2_DOWN_RATIO | PWR_CTRL1_CORE1_DOWN_RATIO |\n" - "+\t\tPWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |\n" - "+\t\tPWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |\n" - "+\t\tPWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);\n" - "+\t__raw_writel(tmp, reg_base + PWR_CTRL1);\n" - "+\n" - "+\t/*\n" - "+\t * Enable arm clock up (on exiting idle). Set arm divider\n" - "+\t * ratios when not in idle along with the standby duration\n" - "+\t * ratios.\n" - "+\t */\n" - "+\ttmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN |\n" - "+\t\tPWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL |\n" - "+\t\tPWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO);\n" - "+\t__raw_writel(tmp, reg_base + PWR_CTRL2);\n" - "+\n" - " \texynos5250_clk_sleep_init();\n" - " \n" - " \tpr_info(\"Exynos5250: clock setup completed, armclk=%ld\\n\",\n" - "-- \n" - 1.9.1 + "Tomasz\n" + "-------------- next part --------------\n" + "A non-text attachment was scrubbed...\n" + "Name: 0001-ARM-EXYNOS-Move-arm-core-power-down-clock-to-exynos5.patch\n" + "Type: text/x-patch\n" + "Size: 6226 bytes\n" + "Desc: not available\n" + URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20140411/1ad9e7d6/attachment.bin> -ba42020f3a8c4c431c0db477d844c4efc9d52881af27c928b89a0f805a4ec1e6 +d4adc3fd4502097585326c5cf8c8e283b315ac35f89fa2d1f2bd2212c04b037c
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