From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?B?Q2hyaXN0aWFuIEvDtm5pZw==?= Subject: Re: 15-rc1: radeon modesetting fails Date: Wed, 16 Apr 2014 12:07:20 +0200 Message-ID: <534E5658.5090404@vodafone.de> References: <20140415070204.GA4806@pd.tnic> <534CFBD7.3070604@amd.com> <20140415120740.GA8306@nazgul.tnic> <534D2F6E.1020608@amd.com> <20140415142454.GA4826@pd.tnic> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="------------080303000802000606070202" Return-path: Received: from pegasos-out.vodafone.de (pegasos-out.vodafone.de [80.84.1.38]) by gabe.freedesktop.org (Postfix) with ESMTP id 515636EA56 for ; Wed, 16 Apr 2014 03:07:41 -0700 (PDT) Received: from localhost (localhost.localdomain [127.0.0.1]) by pegasos-out.vodafone.de (Rohrpostix1 Daemon) with ESMTP id 8B06F2613E1 for ; Wed, 16 Apr 2014 12:07:34 +0200 (CEST) Received: from pegasos-out.vodafone.de ([127.0.0.1]) by localhost (rohrpostix1.prod.vfnet.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Glq1lsFfrBuM for ; Wed, 16 Apr 2014 12:07:29 +0200 (CEST) In-Reply-To: <20140415142454.GA4826@pd.tnic> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Borislav Petkov , =?UTF-8?B?Q2hyaXN0aWFuIEvDtm5pZw==?= Cc: Alex Deucher , Maling list - DRI developers List-Id: dri-devel@lists.freedesktop.org This is a multi-part message in MIME format. --------------080303000802000606070202 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Hi Borislav, thanks for the logs, those were indeed quite helpful. Attached are two patches, the first one tries to solve the problem by=20 increasing the accuracy of the parameters if we don't match exactly and=20 the second improves the logging of the calculation process by dumping a=20 bunch of intermediate values used. Please apply both on top of my drm-fixes-3.15-wip branch you are already=20 using, if the first one doesn't solve the problem then please provide=20 new dmesg logs with drm.debug=3D0xE. Thanks in advance, Christian. Am 15.04.2014 16:24, schrieb Borislav Petkov: > On Tue, Apr 15, 2014 at 03:09:02PM +0200, Christian K=C3=B6nig wrote: >>> Does reverting: >>> http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit= /?id=3D32167016076f714f0e35e287fbead7de0f1fb179 >>> fix the issue? We may need to tweak the pll parameters for older asi= cs. >> Yeah, indeed the most likely cause. Please provide dmesg outputs creat= ed >> with drm.ebug=3D0xe for the old and the new kernel. > Hey, I finally haz 15-rc1+ running here. And I can even see something! > > :-) > > Ok, so I reverted 32167016076f ontop of Christian's drm-fixes-3.15-wip > branch which didn't apply cleanly. So I ended up fixing the conflicts > and got the revert below. > > With it, the machine booted fine, so it looks like the revert worked. > > Christian, I'm sending dmesg outputs in another private mail to you > guys. > > Thanks. --------------080303000802000606070202 Content-Type: text/x-diff; name="0001-drm-radeon-improve-PLL-params-if-we-don-t-match-exac.patch" Content-Disposition: attachment; filename*0="0001-drm-radeon-improve-PLL-params-if-we-don-t-match-exac.pa"; filename*1="tch" Content-Transfer-Encoding: quoted-printable >>From 19de393134c00989b5b1cc5e6dd4ed444a897ace Mon Sep 17 00:00:00 2001 From: =3D?UTF-8?q?Christian=3D20K=3DC3=3DB6nig?=3D Date: Wed, 16 Apr 2014 11:54:21 +0200 Subject: [PATCH 1/2] drm/radeon: improve PLL params if we don't match exa= ctly MIME-Version: 1.0 Content-Type: text/plain; charset=3DUTF-8 Content-Transfer-Encoding: 8bit Otherwise we might be quite off on older chipsets. Signed-off-by: Christian K=C3=B6nig --- drivers/gpu/drm/radeon/radeon_display.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/ra= deon/radeon_display.c index 2f42912..fb3b505 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -865,7 +865,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, unsigned post_div_min, post_div_max, post_div; unsigned ref_div_min, ref_div_max, ref_div; unsigned post_div_best, diff_best; - unsigned nom, den, tmp; + unsigned nom, den; =20 /* determine allowed feedback divider range */ fb_div_min =3D pll->min_feedback_div; @@ -941,22 +941,23 @@ void radeon_compute_pll_avivo(struct radeon_pll *pl= l, ref_div_max =3D min(210 / post_div, ref_div_max); =20 /* get matching reference and feedback divider */ - ref_div =3D max(den / post_div, 1u); - fb_div =3D nom; + ref_div =3D DIV_ROUND_CLOSEST(den, post_div); + fb_div =3D DIV_ROUND_CLOSEST(nom * ref_div * post_div, den); =20 /* we're almost done, but reference and feedback divider might be to large now */ =20 - tmp =3D ref_div; + nom =3D fb_div; + den =3D ref_div; =20 if (fb_div > fb_div_max) { - ref_div =3D ref_div * fb_div_max / fb_div; + ref_div =3D DIV_ROUND_CLOSEST(den * fb_div_max, nom); fb_div =3D fb_div_max; } =20 if (ref_div > ref_div_max) { ref_div =3D ref_div_max; - fb_div =3D nom * ref_div_max / tmp; + fb_div =3D DIV_ROUND_CLOSEST(nom * ref_div_max, den); } =20 /* reduce the numbers to a simpler ratio once more */ --=20 1.9.1 --------------080303000802000606070202 Content-Type: text/x-diff; name="0002-drm-radeon-improve-logging-of-PLL-parameter-calculat.patch" Content-Disposition: attachment; filename*0="0002-drm-radeon-improve-logging-of-PLL-parameter-calculat.pa"; filename*1="tch" Content-Transfer-Encoding: quoted-printable >>From e0e6fa5c0b7df9a3de1784082a878bcfebb8a941 Mon Sep 17 00:00:00 2001 From: =3D?UTF-8?q?Christian=3D20K=3DC3=3DB6nig?=3D Date: Wed, 16 Apr 2014 11:57:28 +0200 Subject: [PATCH 2/2] drm/radeon: improve logging of PLL parameter calcula= tion MIME-Version: 1.0 Content-Type: text/plain; charset=3DUTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Christian K=C3=B6nig --- drivers/gpu/drm/radeon/radeon_display.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/ra= deon/radeon_display.c index fb3b505..037db45 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -820,6 +820,9 @@ static void avivo_reduce_ratio(unsigned *nom, unsigne= d *den, { unsigned tmp; =20 + DRM_DEBUG_KMS("nom: %d den: %d nom_min %d den_min %d\n", + *nom, *den, nom_min, den_min); + /* reduce the numbers to a simpler ratio */ tmp =3D gcd(*nom, *den); *nom /=3D tmp; @@ -876,6 +879,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, fb_div_max *=3D 10; } =20 + DRM_DEBUG_KMS("fb_div_min: %d fb_div_max: %d\n", + fb_div_min, fb_div_max); + /* determine allowed ref divider range */ if (pll->flags & RADEON_PLL_USE_REF_DIV) ref_div_min =3D pll->reference_div; @@ -883,6 +889,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, ref_div_min =3D pll->min_ref_div; ref_div_max =3D pll->max_ref_div; =20 + DRM_DEBUG_KMS("ref_div_min: %d ref_div_max: %d\n", + ref_div_min, ref_div_max); + /* determine allowed post divider range */ if (pll->flags & RADEON_PLL_USE_POST_DIV) { post_div_min =3D pll->post_div; @@ -912,6 +921,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, post_div_max =3D pll->max_post_div; } =20 + DRM_DEBUG_KMS("post_div_min: %d post_div_max: %d\n", + post_div_min, post_div_max); + /* represent the searched ratio as fractional number */ nom =3D pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ? freq : freq / 10; den =3D pll->reference_freq; @@ -980,7 +992,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll, *post_div_p =3D post_div; =20 DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", - freq, *dot_clock_p, *fb_div_p, *frac_fb_div_p, + freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, ref_div, post_div); } =20 --=20 1.9.1 --------------080303000802000606070202 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/dri-devel --------------080303000802000606070202--