Re: [PATCH v4 1/2] SVM: support data breakpoint extension registers

[Boris Ostrovsky <boris.ostrovsky@oracle.com>]

(Sorry for being late).

On 04/16/2014 10:33 AM, Jan Beulich wrote:
> @@ -1451,6 +1551,8 @@ static int svm_msr_read_intercept(unsign
>   
>       switch ( msr )
>       {
> +        unsigned int ecx;
> +
>       case MSR_IA32_SYSENTER_CS:
>           *msr_content = v->arch.hvm_svm.guest_sysenter_cs;
>           break;
> @@ -1526,6 +1628,21 @@ static int svm_msr_read_intercept(unsign
>           vpmu_do_rdmsr(msr, msr_content);
>           break;
>   
> +    case MSR_AMD64_DR0_ADDRESS_MASK:
> +        hvm_cpuid(0x80000001, NULL, NULL, &ecx, NULL);
> +        if ( !test_bit(X86_FEATURE_DBEXT & 31, &ecx) )
> +            goto gpf;
> +        *msr_content = v->arch.hvm_svm.dr_mask[0];
> +        break;
> +
> +    case MSR_AMD64_DR1_ADDRESS_MASK ... MSR_AMD64_DR3_ADDRESS_MASK:
> +        hvm_cpuid(0x80000001, NULL, NULL, &ecx, NULL);
> +        if ( !test_bit(X86_FEATURE_DBEXT & 31, &ecx) )
> +            goto gpf;
> +        *msr_content =
> +            v->arch.hvm_svm.dr_mask[msr - MSR_AMD64_DR1_ADDRESS_MASK + 1];
> +        break;
> +

Can you merge these two cases (here and in write_intercept)? They are 
doing logically the same thing, the only difference is index calculation 
(and you can have a macro or something similar for that).

-boris