From: York Sun <yorksun@freescale.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/4][v7] powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS
Date: Wed, 23 Apr 2014 15:28:40 -0700 [thread overview]
Message-ID: <53583E98.5090300@freescale.com> (raw)
In-Reply-To: <1395166226-23473-1-git-send-email-aneesh.bansal@freescale.com>
On 03/18/2014 11:10 AM, Aneesh Bansal wrote:
> Changes:
> 1. L2 cache is being invalidated by Boot ROM code for e6500 core.
> So removing the invalidation from start.S
> 2. Clear the LAW and corresponding configuration for CPC. Boot ROM
> code uses it as hosekeeping area.
> 3. For Secure boot, CPC is configured as SRAM and used as house
> keeping area. This configuration is to be disabled once in uboot.
> Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
> As a result cache invalidation function was getting skipped in
> case CPC is configured as SRAM.This was causing random crashes.
>
> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
> ---
Applied to u-boot-mpc85xx/master, thanks.
York
prev parent reply other threads:[~2014-04-23 22:28 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-18 18:10 [U-Boot] [PATCH 1/4][v7] powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS Aneesh Bansal
2014-04-23 22:28 ` York Sun [this message]
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