From mboxrd@z Thu Jan 1 00:00:00 1970 From: George Cherian Subject: Re: [PATCH 4/6] drivers: net: cpsw: Enable Annexe F Time sync Date: Mon, 28 Apr 2014 18:28:07 +0530 Message-ID: <535E505F.3010302@ti.com> References: <1398658225-25873-1-git-send-email-george.cherian@ti.com> <1398658225-25873-5-git-send-email-george.cherian@ti.com> <20140428075530.GA8371@netboy> Mime-Version: 1.0 Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20140428075530.GA8371@netboy> Sender: linux-kernel-owner@vger.kernel.org To: Richard Cochran Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-omap@vger.kernel.org, davem@davemloft.net, jeffrey.t.kirsher@intel.com, dborkman@redhat.com, ast@plumgrid.com, tklauser@distanz.ch, mpa@pengutronix.de, bhutchings@solarflare.com, zonque@gmail.com, balbi@ti.com, mugunthanvnm@ti.com, t-kristo@ti.com, mturquette@linaro.org, linux@arm.linux.org.uk, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, mark.rutland@arm.com, pawel.moll@arm.com, robh+dt@kernel.org, tony@atomide.com, bcousson@baylibre.com List-Id: linux-omap@vger.kernel.org On 4/28/2014 1:25 PM, Richard Cochran wrote: > On Mon, Apr 28, 2014 at 09:40:23AM +0530, George Cherian wrote: >> Enable the Annex F Time Sync explicitly for DRA7x and AM4372. >> With this enabled the L2 PTP is working. > L2 works fine without this bit. If this is needed for V3 hardware, > then it should have its own code variant. okay > >> while at that rename TS_BIT8 to TS_TTL_NONZERO > Is this bit finally documented for am335x? Not for am335x, but for other SoC's it s documented. > Thanks, > Richard > -- -George From mboxrd@z Thu Jan 1 00:00:00 1970 From: george.cherian@ti.com (George Cherian) Date: Mon, 28 Apr 2014 18:28:07 +0530 Subject: [PATCH 4/6] drivers: net: cpsw: Enable Annexe F Time sync In-Reply-To: <20140428075530.GA8371@netboy> References: <1398658225-25873-1-git-send-email-george.cherian@ti.com> <1398658225-25873-5-git-send-email-george.cherian@ti.com> <20140428075530.GA8371@netboy> Message-ID: <535E505F.3010302@ti.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 4/28/2014 1:25 PM, Richard Cochran wrote: > On Mon, Apr 28, 2014 at 09:40:23AM +0530, George Cherian wrote: >> Enable the Annex F Time Sync explicitly for DRA7x and AM4372. >> With this enabled the L2 PTP is working. > L2 works fine without this bit. If this is needed for V3 hardware, > then it should have its own code variant. okay > >> while at that rename TS_BIT8 to TS_TTL_NONZERO > Is this bit finally documented for am335x? Not for am335x, but for other SoC's it s documented. > Thanks, > Richard > -- -George From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932267AbaD1M7M (ORCPT ); Mon, 28 Apr 2014 08:59:12 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:43130 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932162AbaD1M7J (ORCPT ); Mon, 28 Apr 2014 08:59:09 -0400 Message-ID: <535E505F.3010302@ti.com> Date: Mon, 28 Apr 2014 18:28:07 +0530 From: George Cherian User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:24.0) Gecko/20100101 Thunderbird/24.3.0 MIME-Version: 1.0 To: Richard Cochran CC: , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH 4/6] drivers: net: cpsw: Enable Annexe F Time sync References: <1398658225-25873-1-git-send-email-george.cherian@ti.com> <1398658225-25873-5-git-send-email-george.cherian@ti.com> <20140428075530.GA8371@netboy> In-Reply-To: <20140428075530.GA8371@netboy> Content-Type: text/plain; charset="ISO-8859-1"; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 4/28/2014 1:25 PM, Richard Cochran wrote: > On Mon, Apr 28, 2014 at 09:40:23AM +0530, George Cherian wrote: >> Enable the Annex F Time Sync explicitly for DRA7x and AM4372. >> With this enabled the L2 PTP is working. > L2 works fine without this bit. If this is needed for V3 hardware, > then it should have its own code variant. okay > >> while at that rename TS_BIT8 to TS_TTL_NONZERO > Is this bit finally documented for am335x? Not for am335x, but for other SoC's it s documented. > Thanks, > Richard > -- -George