From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexander Graf Date: Fri, 02 May 2014 08:35:09 +0000 Subject: Re: [PATCH 1/6] KVM: PPC: Book3S PR: Ignore PMU SPRs Message-Id: <536358BD.9030304@suse.de> List-Id: References: <1398788262-3307-1-git-send-email-agraf@suse.de> <1398788262-3307-2-git-send-email-agraf@suse.de> <20140430221259.GD9671@iris.ozlabs.ibm.com> In-Reply-To: <20140430221259.GD9671@iris.ozlabs.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Paul Mackerras Cc: kvm-ppc@vger.kernel.org, kvm@vger.kernel.org On 05/01/2014 12:12 AM, Paul Mackerras wrote: > On Tue, Apr 29, 2014 at 06:17:37PM +0200, Alexander Graf wrote: >> When we expose a POWER8 CPU into the guest, it will start accessing PMU SPRs >> that we don't emulate. Just ignore accesses to them. >> >> Signed-off-by: Alexander Graf > This patch is OK as it stands, but in fact the architecture says that > kernel accesses to unimplemented SPRs are mostly supposed to be no-ops > rather than causing a trap (mostly = excluding mtspr to 0 or mfspr > from 0, 4, 5 or 6). I have a patch to implement that, which I'll > post. I think what we want is a flag similar to x86 where we can force ignore unknown SPRs, but leave it at triggering an interrupt as default. We usually have to be at least aware of unknown SPRs and check that not implementing them is ok for the guest. Debugging a program interrupt because of an unknown SPR is usually a lot easier than debugging a breaking guest because it was using the SPR as storage and we didn't back it by anything. Alex From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexander Graf Subject: Re: [PATCH 1/6] KVM: PPC: Book3S PR: Ignore PMU SPRs Date: Fri, 02 May 2014 10:35:09 +0200 Message-ID: <536358BD.9030304@suse.de> References: <1398788262-3307-1-git-send-email-agraf@suse.de> <1398788262-3307-2-git-send-email-agraf@suse.de> <20140430221259.GD9671@iris.ozlabs.ibm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Cc: kvm-ppc@vger.kernel.org, kvm@vger.kernel.org To: Paul Mackerras Return-path: In-Reply-To: <20140430221259.GD9671@iris.ozlabs.ibm.com> Sender: kvm-ppc-owner@vger.kernel.org List-Id: kvm.vger.kernel.org On 05/01/2014 12:12 AM, Paul Mackerras wrote: > On Tue, Apr 29, 2014 at 06:17:37PM +0200, Alexander Graf wrote: >> When we expose a POWER8 CPU into the guest, it will start accessing PMU SPRs >> that we don't emulate. Just ignore accesses to them. >> >> Signed-off-by: Alexander Graf > This patch is OK as it stands, but in fact the architecture says that > kernel accesses to unimplemented SPRs are mostly supposed to be no-ops > rather than causing a trap (mostly == excluding mtspr to 0 or mfspr > from 0, 4, 5 or 6). I have a patch to implement that, which I'll > post. I think what we want is a flag similar to x86 where we can force ignore unknown SPRs, but leave it at triggering an interrupt as default. We usually have to be at least aware of unknown SPRs and check that not implementing them is ok for the guest. Debugging a program interrupt because of an unknown SPR is usually a lot easier than debugging a breaking guest because it was using the SPR as storage and we didn't back it by anything. Alex