[lm-sensors] New field in MSR_TEMPERATURE_TARGET

[lm-sensors] New field in MSR_TEMPERATURE_TARGET

[Jean Delvare]

Hi Guenter and Ruik,

While checking the latest version of the Intel 64 and IA-32
Architectures Software Developer's Manual [1] in order to fix the recent
regression in the coretemp driver (and the same bug in the turbotstat
tool), I noticed that the most recent Intel processors (Silvermont
Microarchitecture) have a new field in MSR_TEMPERATURE_TARGET:

Bits 29:24
Target Offset (R/W)
Specifies an offset in degrees C to adjust the throttling and
PROCHOT# activation temperature from the default target
specified in TEMPERATURE_TARGET (bits 23:16).

As I understand it, it means two things:

1* We may be returning wrong tempN_crit values for these processors as
the coretemp driver currently does not read this field. Note that it
isn't clear to me if the field holds a signed or unsigned value. If
unsigned, it would mean that one can only set TjMax higher than it's
default value.

2* On these CPUs, we could make tempN_crit writable by the user. I
don't know if it is a good idea, what do you think about it? It could
be argued that this value should be set at boot time by the firmware,
I'm not sure.

If we want to do it, we will need a way to identify Silvermont CPUs so
that we don't make the attributes writable when the Target Offset field
does not exist. Does anyone know how we can identify these CPUs?

[1] http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-system-programming-manual-325384.pdf

-- 
Jean Delvare
SUSE L3 Support

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Re: [lm-sensors] New field in MSR_TEMPERATURE_TARGET

[Guenter Roeck]

On 05/01/2014 03:07 AM, Jean Delvare wrote:
> Hi Guenter and Ruik,
>
> While checking the latest version of the Intel 64 and IA-32
> Architectures Software Developer's Manual [1] in order to fix the recent
> regression in the coretemp driver (and the same bug in the turbotstat
> tool), I noticed that the most recent Intel processors (Silvermont
> Microarchitecture) have a new field in MSR_TEMPERATURE_TARGET:
>
> Bits 29:24
> Target Offset (R/W)
> Specifies an offset in degrees C to adjust the throttling and
> PROCHOT# activation temperature from the default target
> specified in TEMPERATURE_TARGET (bits 23:16).
>
> As I understand it, it means two things:
>
> 1* We may be returning wrong tempN_crit values for these processors as
> the coretemp driver currently does not read this field. Note that it
> isn't clear to me if the field holds a signed or unsigned value. If
> unsigned, it would mean that one can only set TjMax higher than it's
> default value.
>
> 2* On these CPUs, we could make tempN_crit writable by the user. I
> don't know if it is a good idea, what do you think about it? It could
> be argued that this value should be set at boot time by the firmware,
> I'm not sure.
>
> If we want to do it, we will need a way to identify Silvermont CPUs so
> that we don't make the attributes writable when the Target Offset field
> does not exist. Does anyone know how we can identify these CPUs?
>

See:

arch/x86/kernel/cpu/perf_event_intel.c: case 55: /* Atom 22nm "Silvermont" */
arch/x86/kernel/cpu/perf_event_intel.c: case 77: /* Avoton "Silvermont" */

Coretemp returns pretty much unusable temperatures on those CPUs (way too low).
I thought it is the usual accuracy problem with Atom CPUs, but maybe not.
I'll see if I can get hold of one and test this out; maybe that is the reason.

Guenter


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Re: [lm-sensors] New field in MSR_TEMPERATURE_TARGET

[Rudolf Marek]

Hi Khali,

After some google magic I found this:

http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/4th-gen-core-family-mobile-u-y-processor-lines-vol-1-datasheet.pdf

TCC Activation Offset can be used to activate the Adaptive Thermal Monitor at
temperatures lower than TjMAX. It is the preferred thermal protection mechanism 
for Intel Turbo Boost Technology 2.0 operation since ACPI passive throttling 
states will pull the processor out of turbo mode operation when triggered. An 
offset (in degrees Celsius) can be written to the TEMPERATURE_TARGET (0x1A2) 
MSR, bits [29:24]. This value will be subtracted from the value found in bits 
[23:16]. The default offset is 0 °C, where throttling will occur at TjMAX. The 
offset should be set lower than any other protection such as ACPI _PSV trip points.

So yes you could make it writable by user, and this value is always subtracted. 
It looks like this should be taken into account for tempN_crit on the Silvermont 
CPUs.

The Silvermont CPU can be identified in your [1] by looking at 35.4:

Table 35-6 lists model-specific registers (MSRs) for Intel processors based on 
the Silvermont microarchitecture These processors have a CPUID signature with 
DisplayFamily_DisplayModel of  06_37H, 06_4AH, 06_4DH,
06_5AH, and 06_5DH, see Table 35-1.

Thanks
Rudolf



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